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SubjectRe: [PATCH v3] clk: exynos7: Keep aclk_fsys1_200 enabled
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On 09.02.2021 08:48, Stephen Boyd wrote:
> Quoting (2021-01-31 09:04:28)
>> This clock must be always enabled to allow access to any registers in
>> fsys1 CMU. Until proper solution based on runtime PM is applied
>> (similar to what was done for Exynos5433), fix this by calling
>> clk_prepare_enable() directly from clock provider driver.
>>
>> It was observed on Samsung Galaxy S6 device (based on Exynos7420), where
>> UFS module is probed before pmic used to power that device.
>> In this case defer probe was happening and that clock was disabled by
>> UFS driver, causing whole boot to hang on next CMU access.
>>
>
> Does this need a Fixes tag?

That would be

Fixes: 753195a749a6 ("clk: samsung: exynos7: Correct CMU_FSYS1 clocks names")

i.e. commit that introduced definition of the clock. But the fix cannot be
backported that far as build fails with an error:

drivers/clk/samsung/clk-exynos7.c: In function ‘exynos7_clk_top1_init’:
drivers/clk/samsung/clk-exynos7.c:554:21: error: ‘struct clk_onecell_data’ has no member named ‘hws’
554 | hws = ctx->clk_data.hws;

It could only by backported up to:
ecb1f1f7311f ("clk: samsung: Convert common drivers to the new clk_hw API")

We need a different patch to fix it properly in stable kernels.
And dts for board this bugfix patch was prepared is not upstream yet.


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