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SubjectRe: [PATCH v19 3/3] scsi: ufs: Prepare HPB read for cached sub-region
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On Fri, 2021-02-05 at 11:29 +0800, Can Guo wrote:
> > + return ppn_table[offset];
> > +}
> > +
> > +static void
> > +ufshpb_get_pos_from_lpn(struct ufshpb_lu *hpb, unsigned long lpn,
> > int
> > *rgn_idx,
> > + int *srgn_idx, int *offset)
> > +{
> > + int rgn_offset;
> > +
> > + *rgn_idx = lpn >> hpb->entries_per_rgn_shift;
> > + rgn_offset = lpn & hpb->entries_per_rgn_mask;
> > + *srgn_idx = rgn_offset >> hpb->entries_per_srgn_shift;
> > + *offset = rgn_offset & hpb->entries_per_srgn_mask;
> > +}
> > +
> > +static void
> > +ufshpb_set_hpb_read_to_upiu(struct ufshpb_lu *hpb, struct
> > ufshcd_lrb
> > *lrbp,
> > + u32 lpn, u64 ppn, unsigned int
> > transfer_len)
> > +{
> > + unsigned char *cdb = lrbp->cmd->cmnd;
> > +
> > + cdb[0] = UFSHPB_READ;
> > +
> > + put_unaligned_be64(ppn, &cdb[6]);
>
> You are assuming the HPB entries read out by "HPB Read Buffer" cmd
> are
> in Little
> Endian, which is why you are using put_unaligned_be64 here.
>


Actaully, here uses put_unaligned_be64 is no problem. SCSI command
should be big-endian filled. I Think the problem is that geting ppn
from HPB cache in ufshpb_get_ppn().

...
e0000001f: 12 34 56 78 90 fa de ef
...

+
+static u64 ufshpb_get_ppn(struct ufshpb_lu *hpb,
+ struct ufshpb_map_ctx *mctx, int pos, int
*error)
+{
+ u64 *ppn_table; // It s a 64 bits pointer
+ struct page *page;
+ int index, offset;
+
+ index = pos / (PAGE_SIZE / HPB_ENTRY_SIZE);
+ offset = pos % (PAGE_SIZE / HPB_ENTRY_SIZE);
+
+ page = mctx->m_page[index];
+ if (unlikely(!page)) {
+ *error = -ENOMEM;
+ dev_err(&hpb->sdev_ufs_lu->sdev_dev,
+ "error. cannot find page in mctx\n");
+ return 0;
+ }
+
+ ppn_table = page_address(page);
+ if (unlikely(!ppn_table)) {
+ *error = -ENOMEM;
+ dev_err(&hpb->sdev_ufs_lu->sdev_dev,
+ "error. cannot get ppn_table\n");
+ return 0;
+ }
+
+ return ppn_table[offset];
+}




> this assumption
> is not right for all the other flash vendors - HPB entries read out
> by
> "HPB Read Buffer"
> cmd may come in Big Endian, if so, their random read performance are
> screwed.
> Actually, I have seen at least two flash vendors acting so. I had to
> modify this line
> to get the code work properly on my setups.
>
> Meanwhile, in your cover letter, you mentioned that the performance
> data
> is collected
> on a UFS2.1 device. Please re-collect the data on a real UFS3.1
> device
> and let me
> know the part number. Otherwise, the data is not quite convincing to
> us.
>
> Regards,
> Can Guo.

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