Messages in this thread | | | Date | Sat, 6 Feb 2021 15:40:04 -0800 | From | Jakub Kicinski <> | Subject | Re: [PATCH v8 net-next 02/15] dts: marvell: add CM3 SRAM memory to cp11x ethernet device tree |
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On Sat, 6 Feb 2021 18:45:48 +0200 stefanc@marvell.com wrote: > From: Konstantin Porotchkin <kostap@marvell.com> > > CM3 SRAM address space would be used for Flow Control configuration. > > Signed-off-by: Stefan Chulski <stefanc@marvell.com> > Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Isn't there are requirement to CC the DT mailing list and Rob on all device tree patches? Maybe someone can clarify I know it's required when adding bindings..
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