Messages in this thread | | | Subject | Re: [PATCH v19 08/25] x86/mm: Introduce _PAGE_COW | From | "Yu, Yu-cheng" <> | Date | Fri, 5 Feb 2021 10:41:52 -0800 |
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On 2/4/2021 12:27 PM, Dave Hansen wrote: > On 2/4/21 12:19 PM, Kees Cook wrote: >>> (e) A page where the processor observed a Write=1 PTE, started a write, set >>> Dirty=1, but then observed a Write=0 PTE. That's possible today, but >>> will not happen on processors that support shadow stack. >> What happens for "e" with/without CET? It sounds like direct writes to >> such pages will be (correctly) rejected by the MMU? > > A page fault would be generated regardless of CET support. > > If CET were not around, the fault would be reported as a present, write > fault. > > If this happened and CET were around (which shouldn't happen in > practice, it means we have a hardware issue) a page fault exception is > generated.
Thanks for the clarification. With or without CET, direct write to Write=0, Dirty=1 PTE triggers page fault.
> Yu-cheng, I'm not sure there's enough debugging around to > tell us if this happens. Would we even notice?
That potential hardware issue is, on a CET-capable system, a processor writes to a Write=1, Dirty=0 page, and then observes the PTE is Write=0, Dirty=1. Let me think about it...
Thanks!
-- Yu-cheng
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