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    Subject[PATCH 5.10 10/57] iommu/io-pgtable-arm: Support coherency for Mali LPAE
    Date
    From: Robin Murphy <robin.murphy@arm.com>

    commit 728da60da7c1ec1e21ae64648e376666de3c279c upstream.

    Midgard GPUs have ACE-Lite master interfaces which allows systems to
    integrate them in an I/O-coherent manner. It seems that from the GPU's
    viewpoint, the rest of the system is its outer shareable domain, and so
    even when snoop signals are wired up, they are only emitted for outer
    shareable accesses. As such, setting the TTBR_SHARE_OUTER bit does
    indeed get coherent pagetable walks working nicely for the coherent
    T620 in the Arm Juno SoC.

    Signed-off-by: Robin Murphy <robin.murphy@arm.com>
    Tested-by: Neil Armstrong <narmstrong@baylibre.com>
    Reviewed-by: Steven Price <steven.price@arm.com>
    Acked-by: Will Deacon <will@kernel.org>
    Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
    Link: https://patchwork.freedesktop.org/patch/msgid/8df778355378127ea7eccc9521d6427e3e48d4f2.1600780574.git.robin.murphy@arm.com
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/iommu/io-pgtable-arm.c | 11 ++++++++++-
    1 file changed, 10 insertions(+), 1 deletion(-)

    --- a/drivers/iommu/io-pgtable-arm.c
    +++ b/drivers/iommu/io-pgtable-arm.c
    @@ -417,7 +417,13 @@ static arm_lpae_iopte arm_lpae_prot_to_p
    << ARM_LPAE_PTE_ATTRINDX_SHIFT);
    }

    - if (prot & IOMMU_CACHE)
    + /*
    + * Also Mali has its own notions of shareability wherein its Inner
    + * domain covers the cores within the GPU, and its Outer domain is
    + * "outside the GPU" (i.e. either the Inner or System domain in CPU
    + * terms, depending on coherency).
    + */
    + if (prot & IOMMU_CACHE && data->iop.fmt != ARM_MALI_LPAE)
    pte |= ARM_LPAE_PTE_SH_IS;
    else
    pte |= ARM_LPAE_PTE_SH_OS;
    @@ -1021,6 +1027,9 @@ arm_mali_lpae_alloc_pgtable(struct io_pg
    cfg->arm_mali_lpae_cfg.transtab = virt_to_phys(data->pgd) |
    ARM_MALI_LPAE_TTBR_READ_INNER |
    ARM_MALI_LPAE_TTBR_ADRMODE_TABLE;
    + if (cfg->coherent_walk)
    + cfg->arm_mali_lpae_cfg.transtab |= ARM_MALI_LPAE_TTBR_SHARE_OUTER;
    +
    return &data->iop;

    out_free_data:

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