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SubjectRe: [PATCH v2 6/7] perf cs-etm: Detect pid in VMID for kernel running at EL2
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On 2/4/21 4:00 AM, Leo Yan wrote:
> On Tue, Feb 02, 2021 at 11:29:47PM +0000, Suzuki Kuruppassery Poulose wrote:
>> On 2/2/21 4:38 PM, Leo Yan wrote:
>>> From: Suzuki K Poulose <suzuki.poulose@arm.com>
>>>
>>> The PID of the task could be traced as VMID when the kernel is running
>>> at EL2. Teach the decoder to look for VMID when the CONTEXTIDR (Arm32)
>>> or CONTEXTIDR_EL1 (Arm64) is invalid but we have a valid VMID.
>>>
>>> Cc: Mike Leach <mike.leach@linaro.org>
>>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>>> Cc: Al Grant <al.grant@arm.com>
>>> Co-developed-by: Leo Yan <leo.yan@linaro.org>
>>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>>> Signed-off-by: Leo Yan <leo.yan@linaro.org>
>>> ---
>>> .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 32 ++++++++++++++++---
>>> 1 file changed, 28 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
>>> index 3f4bc4050477..fb2a163ff74e 100644
>>> --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
>>> +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
>>> @@ -6,6 +6,7 @@
>>> * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
>>> */
>>> +#include <linux/coresight-pmu.h>
>>> #include <linux/err.h>
>>> #include <linux/list.h>
>>> #include <linux/zalloc.h>
>>> @@ -491,13 +492,36 @@ cs_etm_decoder__set_tid(struct cs_etm_queue *etmq,
>>> const ocsd_generic_trace_elem *elem,
>>> const uint8_t trace_chan_id)
>>> {
>>> - pid_t tid;
>>> + pid_t tid = -1;
>>> + u64 pid_fmt;
>>> + int ret;
>>> - /* Ignore PE_CONTEXT packets that don't have a valid contextID */
>>> - if (!elem->context.ctxt_id_valid)
>>> + ret = cs_etm__get_pid_fmt(trace_chan_id, &pid_fmt);
>>> + if (ret)
>>
>> Is this something we can cache in this function ? e.g,
>> static u64 pid_fmt;
>>
>> if (!pid_pfmt)
>> ret = cs_etm__get_pid_fmt(trace_chan_id, &pid_fmt);
>>
>> As all the ETMs will be running at the same exception level.
>
> Sorry that I let you repeated your comments again.
>
> To be honest, I considered this after read your comment in the previous
> series, but I thought it's possible that multiple CPUs have different
> PID format, especially for big.LITTLE arch. After read your suggestion
> again, I think my concern is not valid, even for big.LITTLE, all CPUs
> should run on the same kernel exception level.
>
> So will follow up your suggestion to cache "pid_fmt".

No problem.

>
>>
>>> + return OCSD_RESP_FATAL_SYS_ERR;
>>> +
>>> + /*
>>> + * Process the PE_CONTEXT packets if we have a valid contextID or VMID.
>>> + * If the kernel is running at EL2, the PID is traced in CONTEXTIDR_EL2
>>> + * as VMID, Bit ETM_OPT_CTXTID2 is set in this case.
>>> + */
>>> + switch (pid_fmt) {
>>> + case BIT(ETM_OPT_CTXTID):
>>> + if (elem->context.ctxt_id_valid)
>>> + tid = elem->context.context_id;
>>> + break;
>>> + case BIT(ETM_OPT_CTXTID2) | BIT(ETM_OPT_CTXTID):
>>
>> I would rather fix the cs_etm__get_pid_fmt() to return either of these
>> as commented. i.e, ETM_OPT_CTXTID or ETM_OPT_CTXTID2. Thus we don't
>> need the this case.
>
> I explained why I set both bits for ETM_OPT_CTXTID and ETM_OPT_CTXTID2
> in the patch 05/07. Could you take a look for it?

I have responded to the comment in the patch.

>
>> With the above two addressed:
>>
>> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>


Thanks
Suzuki

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