Messages in this thread |  | | Date | Thu, 4 Feb 2021 09:13:36 +0100 | From | Miquel Raynal <> | Subject | Re: [PATCH] mtd: rawnand: Do not check for bad block if bbt is unavailable |
| |
Hi Manivannan,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> wrote on Wed, 03 Feb 2021 17:11:31 +0530:
> On 3 February 2021 4:54:22 PM IST, Boris Brezillon <boris.brezillon@collabora.com> wrote: > >On Wed, 03 Feb 2021 16:22:42 +0530 > >Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> wrote: > > > >> On 3 February 2021 3:49:14 PM IST, Boris Brezillon > ><boris.brezillon@collabora.com> wrote: > >> >On Wed, 03 Feb 2021 15:42:02 +0530 > >> >Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> wrote: > >> > > >> >> >> > >> >> >> I got more information from the vendor, Telit. The access to > >the > >> >3rd > >> >> >partition is protected by Trustzone and any access in non > >privileged > >> >> >mode (where Linux kernel runs) causes kernel panic and the device > >> >> >reboots. > >> > > >> >Out of curiosity, is it a per-CS-line thing or is this section > >> >protected on all CS? > >> > > >> > >> Sorry, I didn't get your question. > > > >The qcom controller can handle several chips, each connected through a > >different CS (chip-select) line, right? I'm wondering if the firmware > >running in secure mode has the ability to block access for a specific > >CS line or if all CS lines have the same constraint. That will impact > >the way you describe it in your DT (in one case the secure-region > >property should be under the controller node, in the other case it > >should be under the NAND chip node). > > Right. I believe the implementation is common to all NAND chips so the property should be in the controller node.
Looks weird: do you mean that each of the chips will have a secure area?
|  |