Messages in this thread | | | Date | Fri, 26 Feb 2021 23:55:53 +0530 | From | mdalam@codeauro ... | Subject | Re: [PATCH] mtd: rawnand: qcom: update last code word register |
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On 2021-02-24 22:06, Miquel Raynal wrote: > Hello, > > mdalam@codeaurora.org wrote on Wed, 24 Feb 2021 22:00:05 +0530: > >> On 2021-02-24 12:18, Miquel Raynal wrote: >> > Hello, >> > >> > mdalam@codeaurora.org wrote on Wed, 24 Feb 2021 10:09:48 +0530: >> > >> >> On 2021-02-24 01:13, mdalam@codeaurora.org wrote: >> >> > On 2021-02-23 22:04, Miquel Raynal wrote: >> >> >> Hello, >> >> >> >> Md Sadre Alam <mdalam@codeaurora.org> wrote on Tue, 23 Feb 2021 >> >> >> 01:34:27 +0530: >> >> >> >>> From QPIC version 2.0 onwards new register got added to read last >> >> >> >> a new >> >> >> >>> codeword. This change will add the READ_LOCATION_LAST_CW_n register. >> >> >> >> Add support for this READ_LOCATION_LAST_CW_n register. >> >> >> >>> >>> For first three code word READ_LOCATION_n register will be >> >> >>> use.For last code word READ_LOCATION_LAST_CW_n register will be >> >> >>> use. >> >> >> >> " >> >> >> In the case of QPIC v2, codewords 0, 1 and 2 will be accessed through >> >> >> READ_LOCATION_n, while codeword 3 will be accessed through >> >> >> READ_LOCATION_LAST_CW_n. >> >> >> " >> >> >> >> When I read my own sentence, I feel that there is something wrong. >> >> >> If there are only 4 codewords, I guess a QPIC v2 is able to use >> >> >> READ_LOCATION_3 or READ_LOCATION_LAST_CW_0 interchangeably. Isn't it? >> >> >> >> I guess the point of having these "last_cw_n" registers is to support >> >> >> up to 8 codewords, am I wrong? If this the case, the current patch >> >> >> completely fails doing that I don't get the point of such change. >> >> > >> >> > This register is only use to read last code word. >> >> > >> >> > I have address all the comments from all the previous sub sequent >> >> > patches and pushed >> >> > all patches in only one series. >> >> > >> >> > Please check. >> >> >> The registers READ_LOCATION & READ_LOCATION_LAST are not associated >> with number of code words. >> >> These two registers are used to access the location inside a code >> word. >> > >> > Ok. Can you please explain what is a location then? Or point me to a >> > datasheet that explains it. >> >> The location is the position inside a code word. >> >> > >> > Bottom line question: why having READ_LOCATION_0, _1,... an >> > READ_LOCATION_LAST_0, _1, etc? >> >> READ_LOCATION_0, _1,... are used to extract multiple chunks from a >> code word. >> >> e.g If we wanted to extract first 100 bytes from a code word then >> (0...99) READ_LOCATION_0 will be configured. >> if we wanted to extract next 100 bytes (100...199) then >> READ_LOCATION_1 will be configured. >> >> same way for last code word READ_LOCATION_LAST_0, _1, will be >> used. >> > > Nice explanation, and thanks for the below figures. So I guess there > is some kind of "small SRAM" that is > directly addressable perhaps? > > I think I'm fine with your series now. Just a small nit: next time you > send a series, please update the version number "[PATCH v6]" > (automatically added with the -v6 parameter in git-format-patch). But > no need to resend just for that. >
Thanks Miquel. So now no need to test these patches further. I have already tested these patches on IPQ5018 SoC with mtd_test module & nand-utils tool.
> > Thanks, > Miquèl
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