Messages in this thread Patch in this message | | | From | Konrad Dybcio <> | Subject | [PATCH 2/6] clk: qcom: gcc-sdm660: Set HWCG bit to 1 on some clocks | Date | Sat, 20 Feb 2021 16:56:13 +0100 |
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According to the downstream kernel, some clocks need to have HWCG disabled. Fix it.
Fixes: f2a76a2955c0 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660") Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> --- drivers/clk/qcom/gcc-sdm660.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c index 597800ce1bdf..2bf4e29462e8 100644 --- a/drivers/clk/qcom/gcc-sdm660.c +++ b/drivers/clk/qcom/gcc-sdm660.c @@ -980,6 +980,8 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = { static struct clk_branch gcc_aggre2_ufs_axi_clk = { .halt_reg = 0x75034, .halt_check = BRANCH_HALT, + .hwcg_reg = 0x75034, + .hwcg_bit = 1, .clkr = { .enable_reg = 0x75034, .enable_mask = BIT(0), @@ -1027,6 +1029,8 @@ static struct clk_branch gcc_bimc_gfx_clk = { static struct clk_branch gcc_bimc_hmss_axi_clk = { .halt_reg = 0x48004, .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x48004, + .hwcg_bit = 1, .clkr = { .enable_reg = 0x52004, .enable_mask = BIT(22), @@ -1698,6 +1702,8 @@ static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { static struct clk_branch gcc_mmss_sys_noc_axi_clk = { .halt_reg = 0x9000, .halt_check = BRANCH_HALT, + .hwcg_reg = 0x9000, + .hwcg_bit = 1, .clkr = { .enable_reg = 0x9000, .enable_mask = BIT(0), @@ -1956,6 +1962,8 @@ static struct clk_branch gcc_ufs_ahb_clk = { static struct clk_branch gcc_ufs_axi_clk = { .halt_reg = 0x75008, .halt_check = BRANCH_HALT, + .hwcg_reg = 0x75008, + .hwcg_bit = 1, .clkr = { .enable_reg = 0x75008, .enable_mask = BIT(0), -- 2.30.1
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