Messages in this thread | | | Date | Thu, 18 Feb 2021 10:44:26 +0100 | From | Maxime Ripard <> | Subject | Re: [PATCH] clk: sunxi-ng: v3s: add support for variable rate audio pll output |
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On Thu, Feb 18, 2021 at 05:21:16PM +0800, Icenowy Zheng wrote: > > > 于 2021年2月18日 GMT+08:00 下午5:18:39, Tobias Schramm <t.schramm@manjaro.org> 写到: > >Hi Icenowy, > > > > > We have introducee SDM-based accurate audio PLL on several > >> other SoCs. Some people is quite sensitive about audio-related > >things. > > > > >While it is possible to support 24MHz * 128 / 25 / 5 = 24.576MHz > >without > >delta sigma modulation, matching 22.5792MHz is indeed not possible. I > >read you'd prefer me to use SDM like the other SoCs though? Shall I > >send > >a v2 utilizing SDM? > > Yes, I think so.
Yes I'd rather have consistency about how we deal with this across all SoCs
Maxime [unhandled content-type:application/pgp-signature] | |