lkml.org 
[lkml]   [2021]   [Feb]   [15]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 5.4 41/60] drm/sun4i: tcon: set sync polarity for tcon1 channel
    Date
    From: Jernej Skrabec <jernej.skrabec@siol.net>

    [ Upstream commit 50791f5d7b6a14b388f46c8885f71d1b98216d1d ]

    Channel 1 has polarity bits for vsync and hsync signals but driver never
    sets them. It turns out that with pre-HDMI2 controllers seemingly there
    is no issue if polarity is not set. However, with HDMI2 controllers
    (H6) there often comes to de-synchronization due to phase shift. This
    causes flickering screen. It's safe to assume that similar issues might
    happen also with pre-HDMI2 controllers.

    Solve issue with setting vsync and hsync polarity. Note that display
    stacks with tcon top have polarity bits actually in tcon0 polarity
    register.

    Fixes: 9026e0d122ac ("drm: Add Allwinner A10 Display Engine support")
    Reviewed-by: Chen-Yu Tsai <wens@csie.org>
    Tested-by: Andre Heider <a.heider@gmail.com>
    Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
    Signed-off-by: Maxime Ripard <maxime@cerno.tech>
    Link: https://patchwork.freedesktop.org/patch/msgid/20210209175900.7092-3-jernej.skrabec@siol.net
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/gpu/drm/sun4i/sun4i_tcon.c | 25 +++++++++++++++++++++++++
    drivers/gpu/drm/sun4i/sun4i_tcon.h | 6 ++++++
    2 files changed, 31 insertions(+)

    diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
    index ae7ae432aa4ab..6bf1425e8b0ca 100644
    --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
    +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
    @@ -665,6 +665,30 @@ static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
    SUN4I_TCON1_BASIC5_V_SYNC(vsync) |
    SUN4I_TCON1_BASIC5_H_SYNC(hsync));

    + /* Setup the polarity of multiple signals */
    + if (tcon->quirks->polarity_in_ch0) {
    + val = 0;
    +
    + if (mode->flags & DRM_MODE_FLAG_PHSYNC)
    + val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
    +
    + if (mode->flags & DRM_MODE_FLAG_PVSYNC)
    + val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
    +
    + regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val);
    + } else {
    + /* according to vendor driver, this bit must be always set */
    + val = SUN4I_TCON1_IO_POL_UNKNOWN;
    +
    + if (mode->flags & DRM_MODE_FLAG_PHSYNC)
    + val |= SUN4I_TCON1_IO_POL_HSYNC_POSITIVE;
    +
    + if (mode->flags & DRM_MODE_FLAG_PVSYNC)
    + val |= SUN4I_TCON1_IO_POL_VSYNC_POSITIVE;
    +
    + regmap_write(tcon->regs, SUN4I_TCON1_IO_POL_REG, val);
    + }
    +
    /* Map output pins to channel 1 */
    regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
    SUN4I_TCON_GCTL_IOMAP_MASK,
    @@ -1482,6 +1506,7 @@ static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = {

    static const struct sun4i_tcon_quirks sun8i_r40_tv_quirks = {
    .has_channel_1 = true,
    + .polarity_in_ch0 = true,
    .set_mux = sun8i_r40_tcon_tv_set_mux,
    };

    diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
    index a62ec826ae71e..5bdbaf0847824 100644
    --- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
    +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
    @@ -153,6 +153,11 @@
    #define SUN4I_TCON1_BASIC5_V_SYNC(height) (((height) - 1) & 0x3ff)

    #define SUN4I_TCON1_IO_POL_REG 0xf0
    +/* there is no documentation about this bit */
    +#define SUN4I_TCON1_IO_POL_UNKNOWN BIT(26)
    +#define SUN4I_TCON1_IO_POL_HSYNC_POSITIVE BIT(25)
    +#define SUN4I_TCON1_IO_POL_VSYNC_POSITIVE BIT(24)
    +
    #define SUN4I_TCON1_IO_TRI_REG 0xf4

    #define SUN4I_TCON_ECC_FIFO_REG 0xf8
    @@ -224,6 +229,7 @@ struct sun4i_tcon_quirks {
    bool needs_de_be_mux; /* sun6i needs mux to select backend */
    bool needs_edp_reset; /* a80 edp reset needed for tcon0 access */
    bool supports_lvds; /* Does the TCON support an LVDS output? */
    + bool polarity_in_ch0; /* some tcon1 channels have polarity bits in tcon0 pol register */
    u8 dclk_min_div; /* minimum divider for TCON0 DCLK */

    /* callback to handle tcon muxing options */
    --
    2.27.0


    \
     
     \ /
      Last update: 2021-02-15 17:00    [W:4.142 / U:0.060 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site