Messages in this thread | | | Date | Fri, 12 Feb 2021 10:53:03 -0800 | From | Jakub Kicinski <> | Subject | Re: [PATCH net v1 1/3] net: phy: mscc: adding LCPLL reset to VSC8514 |
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On Fri, 12 Feb 2021 15:06:41 +0100 Bjarni Jonasson wrote: > At Power-On Reset, transients may cause the LCPLL to lock onto a > clock that is momentarily unstable. This is normally seen in QSGMII > setups where the higher speed 6G SerDes is being used. > This patch adds an initial LCPLL Reset to the PHY (first instance) > to avoid this issue. > > Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> > Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> > Fixes: e4f9ba642f0b ("net: phy: mscc: add support for VSC8514 PHY.")
Please make sure each commit builds cleanly with W=1 C=1.
This one appears to not build at all?
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