Messages in this thread | | | From | <> | Subject | [PATCH net-next 0/2] ptp: ptp_clockmatrix: Fix output 1 PPS alignment. | Date | Thu, 11 Feb 2021 23:38:43 -0500 |
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From: Vincent Cheng <vincent.cheng.xh@renesas.com>
This series fixes a race condition that may result in the output clock not aligned to internal 1 PPS clock.
Part of device initialization is to align the rising edge of output clocks to the internal rising edge of the 1 PPS clock. If the system APLL and DPLL are not locked when this alignment occurs, the alignment fails and a fixed offset between the internal 1 PPS clock and the output clock occurs.
If a clock is dynamically enabled after power-up, the output clock also needs to be aligned to the internal 1 PPS clock.
Vincent Cheng (2): ptp: ptp_clockmatrix: Add wait_for_sys_apll_dpll_lock. ptp: ptp_clockmatrix: Add alignment of 1 PPS to idtcm_perout_enable.
drivers/ptp/idt8a340_reg.h | 10 +++++ drivers/ptp/ptp_clockmatrix.c | 92 ++++++++++++++++++++++++++++++++++++++++--- drivers/ptp/ptp_clockmatrix.h | 17 +++++++- 3 files changed, 112 insertions(+), 7 deletions(-)
-- 2.7.4
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