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SubjectRe: [PATCH v2 02/12] dts: mvebu: Update A8K AP806/AP807 SDHCI settings
On Wed, Feb 10, 2021 at 04:09:39PM +0200, kostap@marvell.com wrote:
> From: Konstantin Porotchkin <kostap@marvell.com>
>
> Select the AP SDHCI PHY slow mode for AP806 die only (move it
> from armada-ap80x.dtsi to armada-ap806.dtsi). This will allow
> running AP807 based devices at HS400 speed.
> Remove Ap SDHCI slow mode property from MacchiatoBin board DTS
> since it is already selected on the SoC level.
>
> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

Acked-by: Russell King <rmk+kernel@armlinux.org.uk>

> ---
> arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi | 5 -----
> arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 12 ++++++++++++
> arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 1 -
> 3 files changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
> index 73733b4126e2..69653de998e2 100644
> --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
> @@ -109,11 +109,6 @@
>
> &ap_sdhci0 {
> bus-width = <8>;
> - /*
> - * Not stable in HS modes - phy needs "more calibration", so add
> - * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
> - */
> - marvell,xenon-phy-slow-mode;
> no-1-8-v;
> no-sd;
> no-sdio;
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
> index 866628679ac7..828cd539173b 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
> @@ -28,3 +28,15 @@
> reg = <0x278 0xa30>;
> };
> };
> +
> +&ap_sdhci0 {
> + /*
> + * SoC based on AP806 revision A0, A1 and A2 should use slow mode
> + * settings for Ap SDHCI due to HW Erratum HWE-7296210
> + * AP806 revesion B0 and later has this erratum fixed and the slow
> + * mode could be removed in board DTS:
> + * /delete-property/marvell,xenon-phy-slow-mode;
> + * Starting from B0 revision, the AP SDHCI can run with HS400 timing.
> + */
> + marvell,xenon-phy-slow-mode;
> +};
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
> index 12e477f1aeb9..edd6131a0587 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
> @@ -257,7 +257,6 @@
> clock-names = "core";
> clocks = <&ap_clk 4>;
> dma-coherent;
> - marvell,xenon-phy-slow-mode;
> status = "disabled";
> };
>
> --
> 2.17.1
>
>

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