Messages in this thread | | | Subject | Re: [PATCH] pinctrl: imx: imx8mm: fix pad offset of SD1_DATA0 pin | From | Claudius Heine <> | Date | Thu, 11 Feb 2021 11:15:09 +0100 |
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Hi,
can you please add:
Fixes: c1c9d41319c3 ("dt-bindings: imx: Add pinctrl binding doc for imx8mm")
to the commit message.
regards, Claudius
On 2021-02-11 10:54, Claudius Heine wrote: > There is a 0 missing in the pad register offset. This patch adds it. > > Signed-off-by: Claudius Heine <ch@denx.de> > --- > arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h > index 5ccc4cc91959d..a003e6af33533 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h > +++ b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h > @@ -124,7 +124,7 @@ > #define MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 > #define MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 > #define MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 > -#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0 > +#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0 > #define MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 > #define MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 > #define MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 >
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