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Subject[PATCH 3/6] MIPS: refactor the runtime coherent vs noncoherent DMA indicators
Date
Replace the global coherentio enum, and the hw_coherentio (fake) boolean
variables with a single boolean dma_default_coherent flag.

Signed-off-by: Christoph Hellwig <hch@lst.de>
---
arch/mips/alchemy/common/setup.c | 3 +--
arch/mips/include/asm/dma-coherence.h | 24 ++++--------------------
arch/mips/kernel/setup.c | 10 ++++------
arch/mips/mm/c-r4k.c | 8 ++------
arch/mips/mti-malta/malta-setup.c | 6 +++---
arch/mips/pci/pci-alchemy.c | 5 ++---
6 files changed, 16 insertions(+), 40 deletions(-)

diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c
index c2da68e7984450..39e5b9cd882b10 100644
--- a/arch/mips/alchemy/common/setup.c
+++ b/arch/mips/alchemy/common/setup.c
@@ -65,8 +65,7 @@ void __init plat_mem_setup(void)
/* Clear to obtain best system bus performance */
clear_c0_config(1 << 19); /* Clear Config[OD] */

- coherentio = alchemy_dma_coherent() ?
- IO_COHERENCE_ENABLED : IO_COHERENCE_DISABLED;
+ dma_default_coherent = alchemy_dma_coherent();

board_setup(); /* board specific setup */

diff --git a/arch/mips/include/asm/dma-coherence.h b/arch/mips/include/asm/dma-coherence.h
index 5eaa1fcc878a88..846c5ade30d12d 100644
--- a/arch/mips/include/asm/dma-coherence.h
+++ b/arch/mips/include/asm/dma-coherence.h
@@ -9,30 +9,14 @@
#ifndef __ASM_DMA_COHERENCE_H
#define __ASM_DMA_COHERENCE_H

-enum coherent_io_user_state {
- IO_COHERENCE_DEFAULT,
- IO_COHERENCE_ENABLED,
- IO_COHERENCE_DISABLED,
-};
-
-#if defined(CONFIG_DMA_PERDEV_COHERENT)
-/* Don't provide (hw_)coherentio to avoid misuse */
-#elif defined(CONFIG_DMA_MAYBE_COHERENT)
-extern enum coherent_io_user_state coherentio;
-extern int hw_coherentio;
-
+#ifdef CONFIG_DMA_MAYBE_COHERENT
+extern bool dma_default_coherent;
static inline bool dev_is_dma_coherent(struct device *dev)
{
- return coherentio == IO_COHERENCE_ENABLED ||
- (coherentio == IO_COHERENCE_DEFAULT && hw_coherentio);
+ return dma_default_coherent;
}
#else
-#ifdef CONFIG_DMA_NONCOHERENT
-#define coherentio IO_COHERENCE_DISABLED
-#else
-#define coherentio IO_COHERENCE_ENABLED
+#define dma_default_coherent (!IS_ENABLED(CONFIG_DMA_NONCOHERENT))
#endif
-#define hw_coherentio 0
-#endif /* CONFIG_DMA_MAYBE_COHERENT */

#endif
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 7e1f8e2774373d..aef418e6e65879 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -807,14 +807,12 @@ arch_initcall(debugfs_mips);
#endif

#ifdef CONFIG_DMA_MAYBE_COHERENT
-/* User defined DMA coherency from command line. */
-enum coherent_io_user_state coherentio = IO_COHERENCE_DEFAULT;
-EXPORT_SYMBOL_GPL(coherentio);
-int hw_coherentio; /* Actual hardware supported DMA coherency setting. */
+bool dma_default_coherent;
+EXPORT_SYMBOL_GPL(dma_default_coherent);

static int __init setcoherentio(char *str)
{
- coherentio = IO_COHERENCE_ENABLED;
+ dma_default_coherent = true;
pr_info("Hardware DMA cache coherency (command line)\n");
return 0;
}
@@ -822,7 +820,7 @@ early_param("coherentio", setcoherentio);

static int __init setnocoherentio(char *str)
{
- coherentio = IO_COHERENCE_DISABLED;
+ dma_default_coherent = true;
pr_info("Software DMA cache coherency (command line)\n");
return 0;
}
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 4f976d687ab007..58afbc3e4ada03 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1913,15 +1913,11 @@ void r4k_cache_init(void)
__local_flush_icache_user_range = local_r4k_flush_icache_user_range;

#ifdef CONFIG_DMA_NONCOHERENT
-#ifdef CONFIG_DMA_MAYBE_COHERENT
- if (coherentio == IO_COHERENCE_ENABLED ||
- (coherentio == IO_COHERENCE_DEFAULT && hw_coherentio)) {
+ if (dma_default_coherent) {
_dma_cache_wback_inv = (void *)cache_noop;
_dma_cache_wback = (void *)cache_noop;
_dma_cache_inv = (void *)cache_noop;
- } else
-#endif /* CONFIG_DMA_MAYBE_COHERENT */
- {
+ } else {
_dma_cache_wback_inv = r4k_dma_cache_wback_inv;
_dma_cache_wback = r4k_dma_cache_wback_inv;
_dma_cache_inv = r4k_dma_cache_inv;
diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
index 4caff9e3b45637..1cdcb76d393ed1 100644
--- a/arch/mips/mti-malta/malta-setup.c
+++ b/arch/mips/mti-malta/malta-setup.c
@@ -98,7 +98,7 @@ static void __init plat_setup_iocoherency(void)
if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
pr_info("Enabled Bonito CPU coherency\n");
- hw_coherentio = 1;
+ dma_default_coherent = true;
}
if (strstr(fw_getcmdline(), "iobcuncached")) {
BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
@@ -118,12 +118,12 @@ static void __init plat_setup_iocoherency(void)
pr_info("CMP IOCU detected\n");
cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0));
if (cfg & ROCIT_CONFIG_GEN0_PCI_IOCU)
- hw_coherentio = 1;
+ dma_default_coherent = true;
else
pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
}

- if (hw_coherentio)
+ if (dma_default_coherent)
pr_info("Hardware DMA cache coherency enabled\n");
else
pr_info("Software DMA cache coherency enabled\n");
diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c
index 7285b5667568ef..54c86b40d30498 100644
--- a/arch/mips/pci/pci-alchemy.c
+++ b/arch/mips/pci/pci-alchemy.c
@@ -429,9 +429,8 @@ static int alchemy_pci_probe(struct platform_device *pdev)
ctx->alchemy_pci_ctrl.io_map_base = (unsigned long)virt_io;

/* Au1500 revisions older than AD have borked coherent PCI */
- if ((alchemy_get_cputype() == ALCHEMY_CPU_AU1500) &&
- (read_c0_prid() < 0x01030202) &&
- (coherentio == IO_COHERENCE_DISABLED)) {
+ if (alchemy_get_cputype() == ALCHEMY_CPU_AU1500 &&
+ read_c0_prid() < 0x01030202 && !dma_default_coherent) {
val = __raw_readl(ctx->regs + PCI_REG_CONFIG);
val |= PCI_CONFIG_NC;
__raw_writel(val, ctx->regs + PCI_REG_CONFIG);
--
2.29.2
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