Messages in this thread | | | Subject | Re: [PATCH v6 02/15] clk: tegra: Don't enable PLLE HW sequencer at init | From | Stephen Boyd <> | Date | Wed, 10 Feb 2021 19:06:17 -0800 |
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Quoting JC Kuo (2021-01-19 00:55:33) > PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware > power sequencers' output to enable/disable PLLE. PLLE hardware power > sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers > are enabled. > > Signed-off-by: JC Kuo <jckuo@nvidia.com> > Acked-by: Thierry Reding <treding@nvidia.com> > ---
Acked-by: Stephen Boyd <sboyd@kernel.org>
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