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SubjectRe: [PATCH v3 1/4] clk: axi-clkgen: replace ARCH dependencies with driver deps
On Mon, Feb 01, 2021 at 05:12:42PM +0200, Alexandru Ardelean wrote:
> The intent is to be able to run this driver to access the IP core in setups
> where FPGA board is also connected via a PCIe bus. In such cases the number
> of combinations explodes, where the host system can be an x86 with Xilinx
> Zynq/ZynqMP/Microblaze board connected via PCIe.
> Or even a ZynqMP board with a ZynqMP/Zynq/Microblaze connected via PCIe.
>
> To accommodate for these cases, this change removes the limitation for this
> driver to be compilable only on Zynq/Microblaze architectures.
> And adds dependencies on the mechanisms required by the driver to work (OF
> and HAS_IOMEM).
>
> Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Reviewed-by: Moritz Fischer <mdf@kernel.org>
> ---
> drivers/clk/Kconfig | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 85856cff506c..cee1d4e657bc 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -247,7 +247,8 @@ config CLK_TWL6040
>
> config COMMON_CLK_AXI_CLKGEN
> tristate "AXI clkgen driver"
> - depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST
> + depends on HAS_IOMEM || COMPILE_TEST
> + depends on OF
> help
> Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
> FPGAs. It is commonly used in Analog Devices' reference designs.
> --
> 2.17.1
>

Thanks,
Moritz

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