lkml.org 
[lkml]   [2021]   [Dec]   [26]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 3/3 v2] arm64: dts: renesas: add MOST device
    Date
    This patch adds mlp device to dtsi files for R-Car Gen3 SoCs that have
    it.

    Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
    ---
    Change from v1:
    - fix power domain ids so all dtbs build properly

    arch/arm64/boot/dts/renesas/r8a77951.dtsi | 13 +++++++++++++
    arch/arm64/boot/dts/renesas/r8a77960.dtsi | 13 +++++++++++++
    arch/arm64/boot/dts/renesas/r8a77961.dtsi | 13 +++++++++++++
    arch/arm64/boot/dts/renesas/r8a77965.dtsi | 13 +++++++++++++
    arch/arm64/boot/dts/renesas/r8a77990.dtsi | 13 +++++++++++++
    arch/arm64/boot/dts/renesas/r8a77995.dtsi | 13 +++++++++++++
    6 files changed, 78 insertions(+)

    diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi
    index 1768a3e6bb8d..179d860ab9c3 100644
    --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi
    +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi
    @@ -2412,6 +2412,19 @@ ssi9: ssi-9 {
    };
    };

    + mlp: mlp@ec520000 {
    + compatible = "renesas,rcar-gen3-mlp";
    + reg = <0 0xec520000 0 0x800>;
    + interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>;
    + clocks = <&cpg CPG_MOD 802>;
    + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
    + status = "disabled";
    + };
    +
    audma0: dma-controller@ec700000 {
    compatible = "renesas,dmac-r8a7795",
    "renesas,rcar-dmac";
    diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
    index 2bd8169735d3..1e90e848d2c8 100644
    --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi
    +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
    @@ -2284,6 +2284,19 @@ ssiu97: ssiu-51 {
    };
    };

    + mlp: mlp@ec520000 {
    + compatible = "renesas,rcar-gen3-mlp";
    + reg = <0 0xec520000 0 0x800>;
    + interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>;
    + clocks = <&cpg CPG_MOD 802>;
    + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
    + status = "disabled";
    + };
    +
    audma0: dma-controller@ec700000 {
    compatible = "renesas,dmac-r8a7796",
    "renesas,rcar-dmac";
    diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
    index a34d5b1d6431..eb70b601191b 100644
    --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi
    +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
    @@ -2128,6 +2128,19 @@ ssiu97: ssiu-51 {
    };
    };

    + mlp: mlp@ec520000 {
    + compatible = "renesas,rcar-gen3-mlp";
    + reg = <0 0xec520000 0 0x800>;
    + interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>;
    + clocks = <&cpg CPG_MOD 802>;
    + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
    + status = "disabled";
    + };
    +
    audma0: dma-controller@ec700000 {
    compatible = "renesas,dmac-r8a77961",
    "renesas,rcar-dmac";
    diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
    index 08df75606430..293021f59818 100644
    --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
    +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
    @@ -2147,6 +2147,19 @@ ssi9: ssi-9 {
    };
    };

    + mlp: mlp@ec520000 {
    + compatible = "renesas,rcar-gen3-mlp";
    + reg = <0 0xec520000 0 0x800>;
    + interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>;
    + clocks = <&cpg CPG_MOD 802>;
    + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
    + status = "disabled";
    + };
    +
    audma0: dma-controller@ec700000 {
    compatible = "renesas,dmac-r8a77965",
    "renesas,rcar-dmac";
    diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
    index 0ea300a8147d..232391fd0751 100644
    --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
    +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
    @@ -1682,6 +1682,19 @@ ssi9: ssi-9 {
    };
    };

    + mlp: mlp@ec520000 {
    + compatible = "renesas,rcar-gen3-mlp";
    + reg = <0 0xec520000 0 0x800>;
    + interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>;
    + clocks = <&cpg CPG_MOD 802>;
    + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
    + status = "disabled";
    + };
    +
    audma0: dma-controller@ec700000 {
    compatible = "renesas,dmac-r8a77990",
    "renesas,rcar-dmac";
    diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
    index 16ad5fc23a67..33d9ed431d9c 100644
    --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
    +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
    @@ -1132,6 +1132,19 @@ ssi4: ssi-4 {
    };
    };

    + mlp: mlp@ec520000 {
    + compatible = "renesas,rcar-gen3-mlp";
    + reg = <0 0xec520000 0 0x800>;
    + interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>;
    + clocks = <&cpg CPG_MOD 802>;
    + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
    + status = "disabled";
    + };
    +
    audma0: dma-controller@ec700000 {
    compatible = "renesas,dmac-r8a77995",
    "renesas,rcar-dmac";
    --
    2.30.2
    \
     
     \ /
      Last update: 2021-12-26 16:35    [W:4.395 / U:0.016 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site