Messages in this thread Patch in this message | | | Date | Mon, 22 Nov 2021 08:06:56 +0100 | Subject | Re: [PATCH] mtd: spi-nor: mt25qu: Ignore 6th ID byte | From | Alexander Sverdlin <> |
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Hi!
On 19/11/2021 22:19, Michael Walle wrote: >> Ignore 6th ID byte, secure version of mt25qu256a has 0x73 as 6th byte. > > What is the secure version? What is the difference? Do you have some > links to datasheets for both?
For instance: https://www.micron.com/products/nor-flash/serial-nor-flash/part-catalog/mt25qu256aba1ew7-0sit https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qljs_u_256_aba_0.pdf?rev=594079234c1b496496b062c21ce162d6
https://www.micron.com/products/nor-flash/serial-nor-flash/part-catalog/mt25qu256aba8e12-1sit https://media-www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-a/mt25q_qljs_u_256_aba_0.pdf?rev=594079234c1b496496b062c21ce162d6
But the differences are in "MT25Q Security Addendum": "The additional protection features available on the secure MT25Q device include a lock status register bit, top/bottom block address protection lock, volatile configuration lock register at power up, protection management register lock, and a nonvolatile configuration lock register." This is only available under NDA from Micron.
However as long as one doesn't use these security features, it appears compatible with non-secure version. That's why just ignoring the non-standard configuration allows to support it.
> Also please provide the SFDP data for this flash, see [1].
sfdp: 53464450060101ff00060110300000ff84000102800000ffffffffffffff ffffffffffffffffffffffffffffffffffffe520fbffffffff0f29eb276b 273b27bbffffffffffff27bbffff29eb0c2010d80f520000244a99008b8e 03d4ac0127387a757a75fbbdd55c4a0f82ff81bd3d36ffffffffffffffff ffffffffffffffffffe7ffff21dcffff
md5sum: 5ea738216f68c9f98987bb3725699a32
jedec_id: 20bb191044
partname: mt25qu256a
manufacturer: st
(But last 3 do not make sense to me, as they come from the table I modify, not from the chip itself). Further, I don't have 512Mbit chip to provide SFDP for it.
> [1] https://lore.kernel.org/linux-mtd/7038f037de3e224016d269324517400d@walle.cc/ > >> >> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> >> --- >> drivers/mtd/spi-nor/micron-st.c | 12 ++++++------ >> 1 file changed, 6 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c >> index f3d19b7..509a732 100644 >> --- a/drivers/mtd/spi-nor/micron-st.c >> +++ b/drivers/mtd/spi-nor/micron-st.c >> @@ -155,9 +155,9 @@ static const struct flash_info st_parts[] = { >> { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | >> USE_FSR | SPI_NOR_DUAL_READ | >> SPI_NOR_QUAD_READ) }, >> - { "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512, >> - SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | >> - SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, >> + { "mt25qu256a", INFO(0x20bb19, 0x1044, 64 * 1024, 512, >> + SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | >> + SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, >> { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, >> SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, >> { "mt25ql512a", INFO6(0x20ba20, 0x104400, 64 * 1024, 1024, >> @@ -167,9 +167,9 @@ static const struct flash_info st_parts[] = { >> SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | >> SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | >> SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) }, >> - { "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024, >> - SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | >> - SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, >> + { "mt25qu512a", INFO(0x20bb20, 0x1044, 64 * 1024, 1024, >> + SECT_4K | USE_FSR | SPI_NOR_DUAL_READ | >> + SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, >> { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, >> SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | >> SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
-- Best regards, Alexander Sverdlin.
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