Messages in this thread | | | Date | Fri, 19 Nov 2021 05:19:50 -0600 | Subject | Re: [PATCH] cpufreq: intel_pstate: ITMT support for overclocked system | From | Michael Larabel <> |
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On 11/18/21 23:18, Srinivas Pandruvada wrote: > On systems with overclocking enabled, CPPC Highest Performance can be > hard coded to 0xff. In this case even if we have cores with different > highest performance, ITMT can't be enabled as the current implementation > depends on CPPC Highest Performance. > > On such systems we can use MSR_HWP_CAPABILITIES maximum performance field > when CPPC.Highest Performance is 0xff. > > Due to legacy reasons, we can't solely depend on MSR_HWP_CAPABILITIES as > in some older systems CPPC Highest Performance is the only way to identify > different performing cores. > > Reported-by: Michael Larabel <Michael@MichaelLarabel.com> > Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> > --- > This patch was tested on one Alder Lake system by enabling Overclocking. > Once overclocking is enabled, we see > $cat /sys/devices/system/cpu/cpu*/acpi_cppc/highest_perf > 255 (P-Cores) > 255 (P-Cores > ... > ... > 255 (E-Cores) > 255 (E-Cores) > The real max performance for CPUs on this system was > 0x40 for P-cores and 0x26 for E-cores. > With this change applied we will see > $cat /proc/sys/kernel/sched_itmt_enabled > 1 > The resultant ITMT priorities > for P-core 0x40, P-core HT sibling 0x10 and E-core 0x26
With this patch I can confirm that now sched_itmt_enabled = 1 and correct highest_perf with the ASUS ROG STRIX Z690-E GAMING WIFI board on the latest BIOS. Thanks.
Tested-by: Michael Larabel <Michael@MichaelLarabel.com>
Michael
> > drivers/cpufreq/intel_pstate.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c > index 815df3daae9d..3106e62ffb25 100644 > --- a/drivers/cpufreq/intel_pstate.c > +++ b/drivers/cpufreq/intel_pstate.c > @@ -338,6 +338,8 @@ static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) > > static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); > > +#define CPPC_MAX_PERF U8_MAX > + > static void intel_pstate_set_itmt_prio(int cpu) > { > struct cppc_perf_caps cppc_perf; > @@ -348,6 +350,14 @@ static void intel_pstate_set_itmt_prio(int cpu) > if (ret) > return; > > + /* > + * On some systems with overclocking enabled, CPPC.highest_perf is hardcoded to 0xff. > + * In this case we can't use CPPC.highest_perf to enable ITMT. > + * In this case we can look at MSR_HWP_CAPABILITIES bits [8:0] to decide. > + */ > + if (cppc_perf.highest_perf == CPPC_MAX_PERF) > + cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached)); > + > /* > * The priorities can be set regardless of whether or not > * sched_set_itmt_support(true) has been called and it is valid to
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