The following changes since commit 3f2401f47d29d669e2cb137709d10dd4c156a02f:

  RISC-V: Add hypervisor extension related CSR defines (2021-10-04 04:54:55 -0400)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-linus-5.16-mw1

for you to fetch changes up to ffa7a9141bb70702744a312f904b190ca064bdd7:

  riscv: defconfig: enable DRM_NOUVEAU (2021-10-27 14:36:09 -0700)

----------------------------------------------------------------
RISC-V Patches for the 5.16 Merge Window, Part 1

* Support for time namespaces in the VDSO, along with some associated
  cleanups.
* Support for building rv32 randconfigs.
* Improvements to the XIP port that allow larger kernels to function
* Various device tree cleanups for both the SiFive and Microchip boards
* A handful of defconfig updates, including enabling Nouveau.

There are also various small cleanups.

----------------------------------------------------------------
Dimitri John Ledkov (1):
      riscv: set default pm_power_off to NULL

Heinrich Schuchardt (1):
      riscv: defconfig: enable DRM_NOUVEAU

Kefeng Wang (1):
      riscv/vdso: Drop unneeded part due to merge issue

Krzysztof Kozlowski (11):
      dt-bindings: mmc: cdns: document Microchip MPFS MMC/SDHCI controller
      riscv: dts: microchip: drop duplicated nodes
      riscv: dts: microchip: fix board compatible
      riscv: dts: microchip: drop duplicated MMC/SDHC node
      riscv: dts: microchip: drop unused pinctrl-names
      riscv: dts: microchip: use vendor compatible for Cadence SD4HC
      riscv: dts: sifive: use only generic JEDEC SPI NOR flash compatible
      riscv: dts: sifive: fix Unleashed board compatible
      riscv: dts: sifive: drop duplicated nodes and properties in sifive
      riscv: dts: microchip: add missing compatibles for clint and plic
      riscv: dts: sifive: add missing compatible for plic

Palmer Dabbelt (3):
      Merge remote-tracking branch 'palmer/riscv-vdso-cleanup' into for-next
      Merge tag 'for-riscv' of https://git.kernel.org/pub/scm/virt/kvm/kvm.git into for-next
      Merge tag 'riscv-sifive-dt-5.16' of git://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux into for-next

Randy Dunlap (1):
      riscv: add rv32 and rv64 randconfig build targets

Tong Tiangen (1):
      riscv/vdso: Add support for time namespaces

Vineet Gupta (1):
      riscv: mm: don't advertise 1 num_asid for 0 asid bits

Vitaly Wool (1):
      riscv: remove .text section size limitation for XIP

 .../devicetree/bindings/mmc/cdns,sdhci.yaml        |   1 +
 arch/riscv/Kconfig                                 |   1 +
 arch/riscv/Makefile                                |  10 +
 .../dts/microchip/microchip-mpfs-icicle-kit.dts    |  18 +-
 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi  |  40 +---
 arch/riscv/boot/dts/sifive/fu540-c000.dtsi         |   2 +-
 .../riscv/boot/dts/sifive/hifive-unleashed-a00.dts |  10 +-
 .../riscv/boot/dts/sifive/hifive-unmatched-a00.dts |   7 +-
 arch/riscv/configs/32-bit.config                   |   2 +
 arch/riscv/configs/64-bit.config                   |   2 +
 arch/riscv/configs/defconfig                       |   7 +-
 arch/riscv/include/asm/page.h                      |   2 +
 arch/riscv/include/asm/pgtable.h                   |   6 +-
 arch/riscv/include/asm/syscall.h                   |   1 +
 arch/riscv/include/asm/vdso.h                      |  13 +-
 arch/riscv/include/asm/vdso/gettimeofday.h         |   7 +
 arch/riscv/kernel/head.S                           |  12 +
 arch/riscv/kernel/reset.c                          |  12 +-
 arch/riscv/kernel/syscall_table.c                  |   1 -
 arch/riscv/kernel/vdso.c                           | 261 +++++++++++++++++----
 arch/riscv/kernel/vdso/vdso.lds.S                  |   6 +-
 arch/riscv/kernel/vmlinux-xip.lds.S                |  10 +-
 arch/riscv/mm/context.c                            |   8 +-
 arch/riscv/mm/init.c                               |   7 +-
 24 files changed, 311 insertions(+), 135 deletions(-)
 create mode 100644 arch/riscv/configs/32-bit.config
 create mode 100644 arch/riscv/configs/64-bit.config