Messages in this thread | | | Date | Thu, 7 Oct 2021 17:10:48 +0100 | From | Catalin Marinas <> | Subject | Re: [PATCH v2 15/17] arm64: Add erratum detection for TRBE write to out-of-range |
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On Tue, Sep 21, 2021 at 02:41:19PM +0100, Suzuki K Poulose wrote: > Arm Neoverse-N2 and Cortex-A710 cores are affected by an erratum where the > trbe, under some circumstances, might write upto 64bytes to an address after > the Limit as programmed by the TRBLIMITR_EL1.LIMIT. This might - > > - Corrupt a page in the ring buffer, which may corrupt trace from a > previous session, consumed by userspace. > - Hit the guard page at the end of the vmalloc area and raise a fault. > > To keep the handling simpler, we always leave the last page from the > range, which TRBE is allowed to write. This can be achieved by ensuring > that we always have more than a PAGE worth space in the range, while > calculating the LIMIT for TRBE. And then the LIMIT pointer can be adjusted > to leave the PAGE (TRBLIMITR.LIMIT -= PAGE_SIZE), out of the TRBE range > while enabling it. This makes sure that the TRBE will only write to an area > within its allowed limit (i.e, [head-head+size]) and we do not have to handle > address faults within the driver. > > Cc: Anshuman Khandual <anshuman.khandual@arm.com> > Cc: Mathieu Poirier <mathieu.poirier@linaro.org> > Cc: Mike Leach <mike.leach@linaro.org> > Cc: Leo Yan <leo.yan@linaro.org> > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
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