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    SubjectRe: [PATCH v2 11/17] arm64: errata: Add workaround for TSB flush failures
    On Tue, Sep 21, 2021 at 02:41:15PM +0100, Suzuki K Poulose wrote:
    > Arm Neoverse-N2 (#2067961) and Cortex-A710 (#2054223) suffers
    > from errata, where a TSB (trace synchronization barrier)
    > fails to flush the trace data completely, when executed from
    > a trace prohibited region. In Linux we always execute it
    > after we have moved the PE to trace prohibited region. So,
    > we can apply the workaround everytime a TSB is executed.
    >
    > The work around is to issue two TSB consecutively.
    >
    > NOTE: This errata is defined as LOCAL_CPU_ERRATUM, implying
    > that a late CPU could be blocked from booting if it is the
    > first CPU that requires the workaround. This is because we
    > do not allow setting a cpu_hwcaps after the SMP boot. The
    > other alternative is to use "this_cpu_has_cap()" instead
    > of the faster system wide check, which may be a bit of an
    > overhead, given we may have to do this in nvhe KVM host
    > before a guest entry.
    >
    > Cc: Will Deacon <will@kernel.org>
    > Cc: Catalin Marinas <catalin.marinas@arm.com>
    > Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
    > Cc: Mike Leach <mike.leach@linaro.org>
    > Cc: Mark Rutland <mark.rutland@arm.com>
    > Cc: Anshuman Khandual <anshuman.khandual@arm.com>
    > Cc: Marc Zyngier <maz@kernel.org>
    > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>

    Acked-by: Catalin Marinas <catalin.marinas@arm.com>

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