Messages in this thread Patch in this message | | | From | kan.liang@linux ... | Subject | [PATCH] perf/x86/msr: Add Sapphire Rapids CPU support | Date | Wed, 6 Oct 2021 13:12:17 -0700 |
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From: Kan Liang <kan.liang@linux.intel.com>
SMI_COUNT MSR is supported on Sapphire Rapids CPU.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com> --- arch/x86/events/msr.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index c853b28..96c775a 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -68,6 +68,7 @@ static bool test_intel(int idx, void *data) case INTEL_FAM6_BROADWELL_D: case INTEL_FAM6_BROADWELL_G: case INTEL_FAM6_BROADWELL_X: + case INTEL_FAM6_SAPPHIRERAPIDS_X: case INTEL_FAM6_ATOM_SILVERMONT: case INTEL_FAM6_ATOM_SILVERMONT_D: -- 2.7.4
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