Messages in this thread | | | From | Naveen Naidu <> | Subject | [PATCH 0/6] MIPS: OCTEON: Remove redundant AER code | Date | Mon, 4 Oct 2021 23:29:26 +0530 |
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e8635b484f64 ("MIPS: Add Cavium OCTEON PCI support.") added MIPS specific code to enable PCIe and AER error reporting (*irrespective of CONFIG_PCIEAER value*) because PCI core didn't do that at the time.
But currently, the PCI core clears and enables the AER status registers. So it's redundant for octeon code to do so. This patch series removes the redundant code from the pci-octeon.c
Currently, the correctable and uncorrectable AER mask registers are not set to their default value when AER service driver is loaded. This defect is also fixed in the "[PATCH 1/6]" in the series.
Please note that "Patch 4/6" is dependent on "Patch 1/6".
Thanks, Naveen Naidu
Naveen Naidu (6): [PATCH 1/6] PCI/AER: Enable COR/UNCOR error reporting in set_device_error_reporting() [PATCH 2/6] MIPS: OCTEON: Remove redundant clearing of AER status registers [PATCH 3/6] MIPS: OCTEON: Remove redundant enable of PCIe normal error reporting [PATCH 4/6] MIPS: OCTEON: Remove redundant enable of COR/UNCOR error [PATCH 5/6] MIPS: OCTEON: Remove redundant ECRC Generation Enable [PATCH 6/6] MIPS: OCTEON: Remove redundant enable of RP error reporting
arch/mips/pci/pci-octeon.c | 50 -------------------------------------- drivers/pci/pcie/aer.c | 13 +++++++++- 2 files changed, 12 insertions(+), 51 deletions(-)
-- 2.25.1
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