lkml.org 
[lkml]   [2021]   [Oct]   [21]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH v15 03/13] PCI: kirin: Use regmap for APB registers
    Date
    The PHY layer need to access APB registers too, for Kirin 970.
    So, place them into a named regmap.

    Acked-by: Xiaowei Song <songxiaowei@hisilicon.com>
    Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
    ---

    To mailbombing on a large number of people, only mailing lists were C/C on the cover.
    See [PATCH v15 00/13] at: https://lore.kernel.org/all/cover.1634812676.git.mchehab+huawei@kernel.org/

    drivers/pci/controller/dwc/pcie-kirin.c | 49 +++++++++++++------------
    1 file changed, 26 insertions(+), 23 deletions(-)

    diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c
    index 91a7c096bf8f..86c13661e02d 100644
    --- a/drivers/pci/controller/dwc/pcie-kirin.c
    +++ b/drivers/pci/controller/dwc/pcie-kirin.c
    @@ -61,8 +61,8 @@ struct kirin_pcie {
    enum pcie_kirin_phy_type type;

    struct dw_pcie *pci;
    + struct regmap *apb;
    struct phy *phy;
    - void __iomem *apb_base;
    void *phy_priv; /* only for PCIE_KIRIN_INTERNAL_PHY */
    };

    @@ -340,25 +340,27 @@ static int hi3660_pcie_phy_init(struct platform_device *pdev,
    * The non-PHY part starts here
    */

    -/* Registers in PCIeCTRL */
    -static inline void kirin_apb_ctrl_writel(struct kirin_pcie *kirin_pcie,
    - u32 val, u32 reg)
    -{
    - writel(val, kirin_pcie->apb_base + reg);
    -}
    -
    -static inline u32 kirin_apb_ctrl_readl(struct kirin_pcie *kirin_pcie, u32 reg)
    -{
    - return readl(kirin_pcie->apb_base + reg);
    -}
    +static const struct regmap_config pcie_kirin_regmap_conf = {
    + .name = "kirin_pcie_apb",
    + .reg_bits = 32,
    + .val_bits = 32,
    + .reg_stride = 4,
    +};

    static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
    struct platform_device *pdev)
    {
    - kirin_pcie->apb_base =
    - devm_platform_ioremap_resource_byname(pdev, "apb");
    - if (IS_ERR(kirin_pcie->apb_base))
    - return PTR_ERR(kirin_pcie->apb_base);
    + struct device *dev = &pdev->dev;
    + void __iomem *apb_base;
    +
    + apb_base = devm_platform_ioremap_resource_byname(pdev, "apb");
    + if (IS_ERR(apb_base))
    + return PTR_ERR(apb_base);
    +
    + kirin_pcie->apb = devm_regmap_init_mmio(dev, apb_base,
    + &pcie_kirin_regmap_conf);
    + if (IS_ERR(kirin_pcie->apb))
    + return PTR_ERR(kirin_pcie->apb);

    return 0;
    }
    @@ -368,13 +370,13 @@ static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie,
    {
    u32 val;

    - val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL0_ADDR);
    + regmap_read(kirin_pcie->apb, SOC_PCIECTRL_CTRL0_ADDR, &val);
    if (on)
    val = val | PCIE_ELBI_SLV_DBI_ENABLE;
    else
    val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;

    - kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL0_ADDR);
    + regmap_write(kirin_pcie->apb, SOC_PCIECTRL_CTRL0_ADDR, val);
    }

    static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie,
    @@ -382,13 +384,13 @@ static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie,
    {
    u32 val;

    - val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL1_ADDR);
    + regmap_read(kirin_pcie->apb, SOC_PCIECTRL_CTRL1_ADDR, &val);
    if (on)
    val = val | PCIE_ELBI_SLV_DBI_ENABLE;
    else
    val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;

    - kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL1_ADDR);
    + regmap_write(kirin_pcie->apb, SOC_PCIECTRL_CTRL1_ADDR, val);
    }

    static int kirin_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn,
    @@ -448,8 +450,9 @@ static void kirin_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,
    static int kirin_pcie_link_up(struct dw_pcie *pci)
    {
    struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
    - u32 val = kirin_apb_ctrl_readl(kirin_pcie, PCIE_APB_PHY_STATUS0);
    + u32 val;

    + regmap_read(kirin_pcie->apb, PCIE_APB_PHY_STATUS0, &val);
    if ((val & PCIE_LINKUP_ENABLE) == PCIE_LINKUP_ENABLE)
    return 1;

    @@ -461,8 +464,8 @@ static int kirin_pcie_start_link(struct dw_pcie *pci)
    struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);

    /* assert LTSSM enable */
    - kirin_apb_ctrl_writel(kirin_pcie, PCIE_LTSSM_ENABLE_BIT,
    - PCIE_APP_LTSSM_ENABLE);
    + regmap_write(kirin_pcie->apb, PCIE_APP_LTSSM_ENABLE,
    + PCIE_LTSSM_ENABLE_BIT);

    return 0;
    }
    --
    2.31.1
    \
     
     \ /
      Last update: 2021-10-21 12:46    [W:2.934 / U:0.904 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site