lkml.org 
[lkml]   [2021]   [Oct]   [15]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
SubjectRe: [PATCH v5 10/15] clk: at91: clk-master: fix prescaler logic
From
Date
On 11/10/2021 at 13:27, Claudiu Beznea wrote:
> When prescaler value read from register is MASTER_PRES_MAX it means
> that the input clock will be divided by 3. Fix the code to reflect
> this.
>
> Fixes: 7a110b9107ed8 ("clk: at91: clk-master: re-factor master clock")
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>

Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>

> ---
> drivers/clk/at91/clk-master.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
> index 6da9ae34313a..e67bcd03a827 100644
> --- a/drivers/clk/at91/clk-master.c
> +++ b/drivers/clk/at91/clk-master.c
> @@ -386,7 +386,7 @@ static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw,
>
> val &= master->layout->mask;
> pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;
> - if (pres == 3 && characteristics->have_div3_pres)
> + if (pres == MASTER_PRES_MAX && characteristics->have_div3_pres)
> pres = 3;
> else
> pres = (1 << pres);
>


--
Nicolas Ferre

\
 
 \ /
  Last update: 2021-10-15 09:59    [W:0.136 / U:2.500 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site