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SubjectRe: [PATCH v5 07/15] clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULL
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On 11/10/2021 at 13:27, Claudiu Beznea wrote:
> Use DIV_ROUND_CLOSEST_ULL() to avoid any inconsistency b/w the rate
> computed in sam9x60_frac_pll_recalc_rate() and the one computed in
> sam9x60_frac_pll_compute_mul_frac().
>
> Fixes: 43b1bb4a9b3e1 ("clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs")
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>

Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>

> ---
> drivers/clk/at91/clk-sam9x60-pll.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
> index 7020d3bf6e13..a73d7c96ce1d 100644
> --- a/drivers/clk/at91/clk-sam9x60-pll.c
> +++ b/drivers/clk/at91/clk-sam9x60-pll.c
> @@ -73,8 +73,8 @@ static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw,
> struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
> struct sam9x60_frac *frac = to_sam9x60_frac(core);
>
> - return (parent_rate * (frac->mul + 1) +
> - ((u64)parent_rate * frac->frac >> 22));
> + return parent_rate * (frac->mul + 1) +
> + DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22));
> }
>
> static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)
>


--
Nicolas Ferre

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