Messages in this thread Patch in this message | | | From | guoren@kernel ... | Subject | [PATCH V4 2/3] dt-bindings: update riscv plic compatible string | Date | Sat, 16 Oct 2021 11:21:59 +0800 |
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From: Guo Ren <guoren@linux.alibaba.com>
Add the compatible string "thead,c900-plic" to the riscv plic bindings to support allwinner d1 SOC which contains c906 core.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Cc: Rob Herring <robh@kernel.org> Cc: Palmer Dabbelt <palmerdabbelt@google.com> Cc: Anup Patel <anup@brainfault.org> Cc: Atish Patra <atish.patra@wdc.com>
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Changes since V4: - Update description in errata style - Update enum suggested by Anup, Heiko, Samuel
Changes since V3: - Rename "c9xx" to "c900" - Add thead,c900-plic in the description section --- .../interrupt-controller/sifive,plic-1.0.0.yaml | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 08d5a57ce00f..272f29540135 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -35,6 +35,12 @@ description: contains a specific memory layout, which is documented in chapter 8 of the SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>. + The C9xx PLIC does not comply with the interrupt claim/completion process defined + by the RISC-V PLIC specification because C9xx PLIC will mask an IRQ when it is + claimed by PLIC driver (i.e. readl(claim) and the IRQ will be unmasked upon + completion by PLIC driver (i.e. writel(claim). This behaviour breaks the handling + of IRQS_ONESHOT by the generic handle_fasteoi_irq() used in the PLIC driver. + maintainers: - Sagar Kadam <sagar.kadam@sifive.com> - Paul Walmsley <paul.walmsley@sifive.com> @@ -46,7 +52,10 @@ properties: - enum: - sifive,fu540-c000-plic - canaan,k210-plic - - const: sifive,plic-1.0.0 + - enmu: + - sifive,plic-1.0.0 + - thead,c900-plic + - allwinner,sun20i-d1-plic reg: maxItems: 1 -- 2.25.1
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