Messages in this thread | | | From | Guo Ren <> | Date | Wed, 13 Oct 2021 11:36:55 +0800 | Subject | Re: [PATCH 0/2] riscv: Add RISC-V svpbmt extension supports |
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Please add V3 in the prefix, I think you need to resend it with PATCH V3 and abandon this one.
On Wed, Oct 13, 2021 at 2:34 AM <wefu@redhat.com> wrote: > > From: Fu Wei <fu.wei@linaro.org> > > This patch follows the standard pure RISC-V Svpbmt extension in > privilege spec to solve the non-coherent SOC DMA synchronization > issues. > > Wei Fu (2): > dt-bindings: riscv: Add mmu-supports with svpbmt > riscv: Add RISC-V svpbmt supports > > .../devicetree/bindings/riscv/cpus.yaml | 5 +++ > arch/riscv/include/asm/fixmap.h | 2 +- > arch/riscv/include/asm/pgtable-64.h | 8 ++-- > arch/riscv/include/asm/pgtable-bits.h | 41 ++++++++++++++++++- > arch/riscv/include/asm/pgtable.h | 39 ++++++++++++++---- > arch/riscv/kernel/cpufeature.c | 32 +++++++++++++++ > arch/riscv/mm/init.c | 5 +++ > 7 files changed, 117 insertions(+), 15 deletions(-) > > -- > 2.25.4 >
-- Best Regards Guo Ren
ML: https://lore.kernel.org/linux-csky/
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