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Subject[PATCH V3 1/2] dt-bindings: update riscv plic compatible string
Date
From: Guo Ren <guoren@linux.alibaba.com>

Add the compatible string "thead,c900-plic" to the riscv plic
bindings to support SOCs with thead,c9xx processor cores.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Palmer Dabbelt <palmerdabbelt@google.com>
Cc: Anup Patel <anup@brainfault.org>
Cc: Atish Patra <atish.patra@wdc.com>

---

Changes since V3:
- Rename "c9xx" to "c900"
- Add thead,c900-plic in the description section
---
.../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 08d5a57ce00f..82629832e5a5 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -35,6 +35,11 @@ description:
contains a specific memory layout, which is documented in chapter 8 of the
SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.

+ While the "thead,c900-plic" would mask IRQ with readl(claim), so it needn't
+ mask/unmask which needed in RISC-V PLIC. When in IRQS_ONESHOT & IRQCHIP_EOI_THREADED
+ path, unnecessary mask operation would cause a blocking irq bug in thead,c900-plic.
+ Because when IRQ is disabled in c900, writel(hwirq, claim) would be invalid.
+
maintainers:
- Sagar Kadam <sagar.kadam@sifive.com>
- Paul Walmsley <paul.walmsley@sifive.com>
@@ -46,6 +51,7 @@ properties:
- enum:
- sifive,fu540-c000-plic
- canaan,k210-plic
+ - thead,c900-plic
- const: sifive,plic-1.0.0

reg:
--
2.25.1
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