Messages in this thread | | | Date | Mon, 11 Oct 2021 11:33:09 +0100 | From | Will Deacon <> | Subject | Re: [PATCH v3 15/17] arm64: Add CNT{P,V}CTSS_EL0 alternatives to cnt{p,v}ct_el0 |
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On Sun, Oct 10, 2021 at 12:43:04PM +0100, Marc Zyngier wrote: > CNTPCTSS_EL0 and CNTVCTSS_EL0 are alternatives to the usual > CNTPCT_EL0 and CNTVCT_EL0 that do not require a previous ISB > to be synchronised (SS stands for Self-Synchronising). > > Use the ARM64_HAS_ECV capability to control alternative sequences > that switch to these low(er)-cost primitives. Note that the > counter access in the VDSO is for now left alone until we decide > whether we want to allow this. > > Signed-off-by: Marc Zyngier <maz@kernel.org> > --- > arch/arm64/include/asm/arch_timer.h | 32 +++++++++++++++++++++-------- > arch/arm64/include/asm/sysreg.h | 3 +++ > 2 files changed, 27 insertions(+), 8 deletions(-) > > diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h > index 519ac1f7f859..33a08fff0f06 100644 > --- a/arch/arm64/include/asm/arch_timer.h > +++ b/arch/arm64/include/asm/arch_timer.h > @@ -64,14 +64,26 @@ DECLARE_PER_CPU(const struct arch_timer_erratum_workaround *, > > static inline notrace u64 arch_timer_read_cntpct_el0(void) > { > - isb(); > - return read_sysreg(cntpct_el0); > + u64 cnt; > + > + asm volatile(ALTERNATIVE("isb\n mrs %x0, cntpct_el0", > + "nop\n" __mrs_s("%x0", SYS_CNTPCTSS_EL0), > + ARM64_HAS_ECV) > + : "=r" (cnt)); > + > + return cnt;
Why do you need to use %x0 instead of just %0 here? Similarly for the other functions you're changing in this file.
Will
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