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    Subject[PATCH v3 1/5] clk: uniphier: Add audio system and video input clock control for PXs3
    Date
    Add clocks for audio subsystem (AIO) and video input subsystem (EXIV) on
    UniPhier PXs3 SoC.

    Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
    ---
    drivers/clk/uniphier/clk-uniphier-sys.c | 2 ++
    1 file changed, 2 insertions(+)

    diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
    index 32b301724183..0ec28ebc39c2 100644
    --- a/drivers/clk/uniphier/clk-uniphier-sys.c
    +++ b/drivers/clk/uniphier/clk-uniphier-sys.c
    @@ -288,6 +288,8 @@ const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
    UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x210c, 7),
    UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x210c, 8),
    UNIPHIER_CLK_GATE("sata-phy", 30, NULL, 0x210c, 21),
    + UNIPHIER_LD11_SYS_CLK_AIO(40),
    + UNIPHIER_LD11_SYS_CLK_EXIV(42),
    /* CPU gears */
    UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
    UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
    --
    2.7.4
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