Messages in this thread | | | Date | Mon, 11 Oct 2021 22:48:02 +0200 | From | Borislav Petkov <> | Subject | Re: linux-next: manual merge of the tip tree with Linus' tree |
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Hi Stephen,
On Mon, Oct 11, 2021 at 01:21:20PM +1100, Stephen Rothwell wrote: > I fixed it up (I just used the version form Linus' tree, but with the > changed return type - see below) and can carry the fix as necessary. This > is now fixed as far as linux-next is concerned, but any non trivial > conflicts should be mentioned to your upstream maintainer when your tree > is submitted for merging. You may also want to consider cooperating > with the maintainer of the conflicting tree to minimise any particularly > complex conflicts.
Thanks, below is Ingo's merge resolution which is identical to yours, AFAICT.
tip/master and tip/auto-latest are updated so you should be able to forget your fixup from now on.
:-)
Cheers!
> diff --cc arch/x86/kernel/fpu/signal.c > index fa17a27390ab,ae51e50f25e8..000000000000 > --- a/arch/x86/kernel/fpu/signal.c > +++ b/arch/x86/kernel/fpu/signal.c > @@@ -377,16 -382,10 +382,16 @@@ static bool __fpu_restore_sig(void __us > } else { > if (__copy_from_user(&fpu->state.fxsave, buf_fx, > sizeof(fpu->state.fxsave))) > - return -EFAULT; > + return false; > > - /* Mask out reserved MXCSR bits. */ > - fpu->state.fxsave.mxcsr &= mxcsr_feature_mask; > + if (IS_ENABLED(CONFIG_X86_64)) { > + /* Reject invalid MXCSR values. */ > + if (fpu->state.fxsave.mxcsr & ~mxcsr_feature_mask) > - return -EINVAL; > ++ return false; > + } else { > + /* Mask invalid bits out for historical reasons (broken hardware). */ > + fpu->state.fxsave.mxcsr &= ~mxcsr_feature_mask; > + } > > /* Enforce XFEATURE_MASK_FPSSE when XSAVE is enabled */ > if (use_xsave())
commit 3ab37cc4d1e3889ddbb44d62a4741754689f6184 (refs/remotes/tip/x86/fpu) Merge: 724fc0248d45 d298b03506d3 Author: Ingo Molnar <mingo@kernel.org> Date: Mon Oct 11 08:53:07 2021 +0200
Merge branch 'x86/urgent' into x86/fpu, to resolve conflict
Resolve the conflict between these two commits:
x86/fpu: 1193f408cd51 ("x86/fpu/signal: Change return type of __fpu_restore_sig() to boolean") x86/urgent: d298b03506d3 ("x86/fpu: Restore the masking out of reserved MXCSR bits")
Conflicts: arch/x86/kernel/fpu/signal.c
Signed-off-by: Ingo Molnar <mingo@kernel.org>
diff --cc arch/x86/kernel/fpu/signal.c index 39c7bae97daf,fa17a27390ab..37dbfed29d75 --- a/arch/x86/kernel/fpu/signal.c +++ b/arch/x86/kernel/fpu/signal.c @@@ -382,11 -377,16 +382,16 @@@ static bool __fpu_restore_sig(void __us } else { if (__copy_from_user(&fpu->state.fxsave, buf_fx, sizeof(fpu->state.fxsave))) - return -EFAULT; + return false; - /* Reject invalid MXCSR values. */ - if (fpu->state.fxsave.mxcsr & ~mxcsr_feature_mask) - return false; + if (IS_ENABLED(CONFIG_X86_64)) { + /* Reject invalid MXCSR values. */ + if (fpu->state.fxsave.mxcsr & ~mxcsr_feature_mask) - return -EINVAL; ++ return false; + } else { + /* Mask invalid bits out for historical reasons (broken hardware). */ + fpu->state.fxsave.mxcsr &= ~mxcsr_feature_mask; + } /* Enforce XFEATURE_MASK_FPSSE when XSAVE is enabled */ if (use_xsave())
-- Regards/Gruss, Boris.
SUSE Software Solutions Germany GmbH, GF: Felix Imendörffer, HRB 36809, AG Nürnberg
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