Messages in this thread | | | From | Vladimir Oltean <> | Subject | Re: [PATCH net v3 1/1] net: pcs: xpcs: fix incorrect CL37 AN sequence | Date | Fri, 1 Oct 2021 10:12:20 +0000 |
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On Fri, Oct 01, 2021 at 10:57:30AM +0100, Russell King (Oracle) wrote: > On Fri, Oct 01, 2021 at 12:19:52AM +0000, Vladimir Oltean wrote: > > static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, unsigned int mode) > > { > > int ret, mdio_ctrl1, old_an_ctrl, an_ctrl, old_dig_ctrl1, dig_ctrl1; > > > > /* Disable SGMII AN in case it is already enabled */ > > mdio_ctrl1 = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL); > > if (mdio_ctrl1 < 0) > > return mdio_ctrl1; > > > > if (mdio_ctrl1 & AN_CL37_EN) { > > ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, > > mdio_ctrl1 & ~AN_CL37_EN); > > if (ret < 0) > > return ret; > > } > > This is fine... > > > if (!(mdio_ctrl1 & AN_CL37_EN) && phylink_autoneg_inband(mode)) { > > ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, > > mdio_ctrl1 | AN_CL37_EN); > > if (ret) > > return ret; > > } > > This is not. If the control register had AN_CL37_EN set initially, then > in the first test above, we clear the bit. However, mdio_ctrl1 will > still contain the bit set. When we get here, we will skip setting the > register bit back to one even if in-band mode was requested. > > As I said in a previous email, at this point there is no reason to check > the previous state, because if it was set on entry, we will have cleared > it, so the register state at this point has the bit clear no matter > what. If we need to set it, then we /always/ need to write it here - it > doesn't matter what the initial state was.
Correct, it should have been:
if (phylink_autoneg_inband(mode)) { ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, mdio_ctrl1 | AN_CL37_EN); if (ret) return ret; }
For the record, just in case this code gets copied anywhere, there's another mistake in my placement of one of the comments.
/* If using in-band autoneg, enable automatic speed/duplex mode change * by HW after SGMII AN complete. * 5) VR_MII_MMD_CTRL Bit(12) [AN_ENABLE] = 1b (Enable SGMII AN) <- this part of the comment */ old_dig_ctrl1 = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1); if (old_dig_ctrl1 < 0) return old_dig_ctrl1;
really belongs here:
/* If using SGMII AN, enable it here */ if (phylink_autoneg_inband(mode)) { ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, mdio_ctrl1 | AN_CL37_EN); if (ret) return ret; }
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