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SubjectRe: [PATCH 3/5] clk: qcom: mmcc-sdm660: Add MDP clock source CXC to MDSS GDSC
Il giorno sab 5 dic 2020 alle ore 06:08 Bjorn Andersson
<bjorn.andersson@linaro.org> ha scritto:
>
> On Sat 26 Sep 08:03 CDT 2020, kholk11@gmail.com wrote:
>
> > From: AngeloGioacchino Del Regno <kholk11@gmail.com>
> >
> > It is required for optimal performance and to avoid MDP stalls to
> > retain mem/periph on GDSC enablement: to achieve this, let's add
> > the required CXC to the MDSS GDSC.
> >
>
> Can you please explain how you came to this conclusion, I don't see the
> reference to the MDP_CLK_SRC in the downstream kernel.
>
> Thanks,
> Bjorn
>
Hey!
I am sure I don't have to go too deep with such an explanation. You know,
downstream is seriously tangled, perhaps that's why you couldn't find how.

By the way, as you can see, here in sdm660-mdss.dtsi we have the
MDP_CLK_SRC clock:
https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/sdm660-mdss.dtsi?h=LA.UM.8.2.r2-03400-sdm660.0#n121

Since downstream uses to set the mem/periph retain in a different way,
here you find
some references to what you're looking for:
https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/drivers/video/fbdev/msm/mdss_mdp.c?h=LA.UM.8.2.r2-03400-sdm660.0#n1555

...of course, also from my own tests, failing to set these flags will
stall the MDP as
soon as we hit a resume from MDP idle power collapse.

P.S.: Sorry for the late reply!
--Angelo

> > Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
> > ---
> > drivers/clk/qcom/mmcc-sdm660.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/clk/qcom/mmcc-sdm660.c b/drivers/clk/qcom/mmcc-sdm660.c
> > index 234aca7c873b..7b1384cf8506 100644
> > --- a/drivers/clk/qcom/mmcc-sdm660.c
> > +++ b/drivers/clk/qcom/mmcc-sdm660.c
> > @@ -2572,6 +2572,8 @@ static struct gdsc mdss_gdsc = {
> > .pd = {
> > .name = "mdss",
> > },
> > + .cxcs = (unsigned int []){ 0x2040 },
> > + .cxc_count = 1,
> > .pwrsts = PWRSTS_OFF_ON,
> > };
> >
> > --
> > 2.28.0
> >

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