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SubjectRe: [PATCH 2/7] dt-bindings: phy: ti,phy-j721e-wiz: Add binding for phy_en_refclk
On Thu, Dec 24, 2020 at 05:12:45PM +0530, Kishon Vijay Abraham I wrote:
> Add DT binding for phy_en_refclk used to route the refclk out of the
> SERDES.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> .../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
> index 4a1f9c27b5f0..14823588bc94 100644
> --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
> +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
> @@ -149,6 +149,19 @@ patternProperties:
> - assigned-clocks
> - assigned-clock-parents
>
> + "^phy-en-refclk$":

Not really a pattern. Move to 'properties'.

> + type: object
> + description: |
> + In order to drive the refclk out from the SERDES (Cadence Torrent),
> + PHY_EN_REFCLK should be set in SERDES_RST of WIZ. Model phy-en-refclk
> + as a clock so that it can be enabled directly or as a parent clock.
> + properties:
> + "#clock-cells":
> + const: 0
> +
> + required:
> + - "#clock-cells"

Though not really any need for a child node here. Just add
'#clock-cells' to the parent node.

> +
> "^serdes@[0-9a-f]+$":
> type: object
> description: |
> --
> 2.17.1
>

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