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    Subject[PATCH v2 2/2] drm/sun4i: tcon: improve DCLK polarity handling
    Date
    From: Giulio Benetti <giulio.benetti@micronovasrl.com>

    It turned out(Maxime suggestion) that bit 26 of SUN4I_TCON0_IO_POL_REG is
    dedicated to invert DCLK polarity and this makes thing really easier than
    before. So let's handle DCLK polarity by adding
    SUN4I_TCON0_IO_POL_DCLK_POSITIVE as bit 26 and activating according to
    bus_flags the same way is done for all the other signals.

    Cc: Maxime Ripard <maxime@cerno.tech>
    Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
    ---
    drivers/gpu/drm/sun4i/sun4i_tcon.c | 20 +-------------------
    drivers/gpu/drm/sun4i/sun4i_tcon.h | 1 +
    2 files changed, 2 insertions(+), 19 deletions(-)

    diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
    index 52598bb0fb0b..30171ccd87e5 100644
    --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
    +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
    @@ -569,26 +569,8 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
    if (info->bus_flags & DRM_BUS_FLAG_DE_LOW)
    val |= SUN4I_TCON0_IO_POL_DE_NEGATIVE;

    - /*
    - * On A20 and similar SoCs, the only way to achieve Positive Edge
    - * (Rising Edge), is setting dclk clock phase to 2/3(240°).
    - * By default TCON works in Negative Edge(Falling Edge),
    - * this is why phase is set to 0 in that case.
    - * Unfortunately there's no way to logically invert dclk through
    - * IO_POL register.
    - * The only acceptable way to work, triple checked with scope,
    - * is using clock phase set to 0° for Negative Edge and set to 240°
    - * for Positive Edge.
    - * On A33 and similar SoCs there would be a 90° phase option,
    - * but it divides also dclk by 2.
    - * Following code is a way to avoid quirks all around TCON
    - * and DOTCLOCK drivers.
    - */
    if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE)
    - clk_set_phase(tcon->dclk, 0);
    -
    - if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
    - clk_set_phase(tcon->dclk, 240);
    + val |= SUN4I_TCON0_IO_POL_DCLK_POSITIVE;

    regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
    SUN4I_TCON0_IO_POL_HSYNC_POSITIVE |
    diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
    index cfbf4e6c1679..0ce71d10a31b 100644
    --- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
    +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
    @@ -113,6 +113,7 @@
    #define SUN4I_TCON0_IO_POL_REG 0x88
    #define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase) ((phase & 3) << 28)
    #define SUN4I_TCON0_IO_POL_DE_NEGATIVE BIT(27)
    +#define SUN4I_TCON0_IO_POL_DCLK_POSITIVE BIT(26)
    #define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE BIT(25)
    #define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE BIT(24)

    --
    2.25.1
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