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    Subject[PATCH v3 02/34] dt-bindings: mailbox: Add Intel VPU IPC mailbox bindings
    Date
    From: Daniele Alessandrelli <daniele.alessandrelli@intel.com>

    Add bindings for the Intel VPU IPC mailbox driver.

    Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
    ---
    .../mailbox/intel,vpu-ipc-mailbox.yaml | 69 +++++++++++++++++++
    MAINTAINERS | 6 ++
    2 files changed, 75 insertions(+)
    create mode 100644 Documentation/devicetree/bindings/mailbox/intel,vpu-ipc-mailbox.yaml

    diff --git a/Documentation/devicetree/bindings/mailbox/intel,vpu-ipc-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/intel,vpu-ipc-mailbox.yaml
    new file mode 100644
    index 000000000000..923a6d619a64
    --- /dev/null
    +++ b/Documentation/devicetree/bindings/mailbox/intel,vpu-ipc-mailbox.yaml
    @@ -0,0 +1,69 @@
    +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    +# Copyright (c) 2020 Intel Corporation
    +%YAML 1.2
    +---
    +$id: "http://devicetree.org/schemas/mailbox/intel,vpu-ipc-mailbox.yaml#"
    +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
    +
    +title: Intel VPU IPC mailbox
    +
    +maintainers:
    + - Daniele Alessandrelli <daniele.alessandrelli@intel.com>
    +
    +description: |
    + Intel VPU SoCs like Keem Bay have hardware FIFOs to enable Inter-Processor
    + Communication (IPC) between the CPU and the VPU.
    +
    + Specifically, there is one HW FIFO for the CPU (aka Application Processor -
    + AP) and one for the VPU. Each FIFO can hold 128 entries of 32 bits each. A
    + "FIFO-not-empty" interrupt is raised every time there is at least a message
    + in the FIFO. The CPU FIFO raises interrupts to the CPU, while the VPU FIFO
    + raises interrupts to VPU. When the CPU wants to send a message to the VPU it
    + writes to the VPU FIFO, similarly, when the VPU want to send a message to the
    + CPU, it writes to the CPU FIFO.
    +
    + Refer to ./mailbox.txt for generic information about mailbox device-tree
    + bindings.
    +
    +properties:
    + compatible:
    + const: intel,vpu-ipc-mailbox
    +
    + reg:
    + items:
    + - description: The CPU FIFO registers
    + - description: The VPU FIFO registers
    +
    + reg-names:
    + items:
    + - const: cpu_fifo
    + - const: vpu_fifo
    +
    + interrupts:
    + items:
    + - description: CPU FIFO-not-empty interrupt
    +
    + "#mbox-cells":
    + const: 1
    +
    +required:
    + - compatible
    + - reg
    + - reg-names
    + - interrupts
    + - "#mbox-cells"
    +
    +additionalProperties: false
    +
    +examples:
    + - |
    + #include <dt-bindings/interrupt-controller/irq.h>
    + #include <dt-bindings/interrupt-controller/arm-gic.h>
    + vpu_ipc_mailbox@203300f0 {
    + compatible = "intel,vpu-ipc-mailbox";
    + #mbox-cells = <1>;
    + reg = <0x203300f0 0x310>,
    + <0x208200f0 0x310>;
    + reg-names = "cpu_fifo", "vpu_fifo";
    + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
    + };
    diff --git a/MAINTAINERS b/MAINTAINERS
    index 992fe3b0900a..2b82526a00dc 100644
    --- a/MAINTAINERS
    +++ b/MAINTAINERS
    @@ -9181,6 +9181,12 @@ L: platform-driver-x86@vger.kernel.org
    S: Maintained
    F: drivers/platform/x86/intel-vbtn.c

    +INTEL VPU IPC MAILBOX
    +M: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
    +M: Mark Gross <mgross@linux.intel.com>
    +S: Supported
    +F: Documentation/devicetree/bindings/mailbox/intel,vpu-ipc-mailbox.yaml
    +
    INTEL WIRELESS 3945ABG/BG, 4965AGN (iwlegacy)
    M: Stanislaw Gruszka <stf_xl@wp.pl>
    L: linux-wireless@vger.kernel.org
    --
    2.17.1
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