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    Subject[PATCH v3 RFC net-next 12/19] net: mvpp2: enable global flow control
    Date
    From: Stefan Chulski <stefanc@marvell.com>

    This patch enables global flow control in FW and in the phylink validate mask.

    Signed-off-by: Stefan Chulski <stefanc@marvell.com>
    ---
    drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 3 +++
    drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 20 +++++++++++++++++++-
    2 files changed, 22 insertions(+), 1 deletion(-)

    diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
    index f34e260..e9625fb 100644
    --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
    +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
    @@ -1022,6 +1022,9 @@ struct mvpp2 {
    /* CM3 SRAM pool */
    struct gen_pool *sram_pool;

    + /* Global TX Flow Control config */
    + bool global_tx_fc;
    +
    bool custom_dma_mask;

    /* Spinlocks for CM3 shared memory configuration */
    diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
    index 64534f0..4d55344 100644
    --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
    +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
    @@ -5963,6 +5963,11 @@ static void mvpp2_phylink_validate(struct phylink_config *config,
    phylink_set(mask, Autoneg);
    phylink_set_port_modes(mask);

    + if (port->priv->global_tx_fc) {
    + phylink_set(mask, Pause);
    + phylink_set(mask, Asym_Pause);
    + }
    +
    switch (state->interface) {
    case PHY_INTERFACE_MODE_10GBASER:
    case PHY_INTERFACE_MODE_XAUI:
    @@ -6981,7 +6986,7 @@ static int mvpp2_probe(struct platform_device *pdev)
    struct resource *res;
    void __iomem *base;
    int i, shared;
    - int err;
    + int err, val;

    priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
    if (!priv)
    @@ -7035,6 +7040,10 @@ static int mvpp2_probe(struct platform_device *pdev)
    return err;
    else if (err)
    dev_warn(&pdev->dev, "Fail to alloc CM3 SRAM\n");
    +
    + /* Enable global Flow Control only if handler to SRAM not NULL */
    + if (priv->cm3_base)
    + priv->global_tx_fc = true;
    }

    if (priv->hw_version != MVPP21 && dev_of_node(&pdev->dev)) {
    @@ -7205,6 +7214,15 @@ static int mvpp2_probe(struct platform_device *pdev)
    goto err_port_probe;
    }

    + /* Enable global flow control. In this stage global
    + * flow control enabled, but still disabled per port.
    + */
    + if (priv->global_tx_fc && priv->hw_version != MVPP21) {
    + val = mvpp2_cm3_read(priv, MSS_FC_COM_REG);
    + val |= FLOW_CONTROL_ENABLE_BIT;
    + mvpp2_cm3_write(priv, MSS_FC_COM_REG, val);
    + }
    +
    mvpp2_dbgfs_init(priv, pdev->name);

    platform_set_drvdata(pdev, priv);
    --
    1.9.1
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