Messages in this thread | | | Subject | Re: [PATCH v3 3/4] arm64: mte: Enable async tag check fault | From | Vincenzo Frascino <> | Date | Mon, 18 Jan 2021 15:39:43 +0000 |
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On 1/18/21 2:48 PM, Vincenzo Frascino wrote: >> Are you aware of cases where the TFSR_EL1 value is read other than by an >> MRS? e.g. are there any cases where checks are elided if TF1 is set? If >> so, we may need the ISB to order the direct write against subsequent >> indirect reads. >> > Thank you for the explanation. I am not aware of any case in which TFSR_EL1 is > read other then by an MRS. Based on the ARM DDI 0487F.c (J1-7626) TF0/TF1 are > always set to '1' without being accessed before. I will check with the > architects for further clarification and if this is correct I will remove the > isb() in the next version. >
I spoke to the architects and I confirm that the isb() can be removed.
-- Regards, Vincenzo
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