Messages in this thread | | | Date | Mon, 18 Jan 2021 14:14:29 +0000 | From | Mark Rutland <> | Subject | Re: [PATCH v3 3/4] arm64: mte: Enable async tag check fault |
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On Mon, Jan 18, 2021 at 01:37:35PM +0000, Vincenzo Frascino wrote: > On 1/18/21 12:57 PM, Catalin Marinas wrote:
> >> + if (tfsr_el1 & SYS_TFSR_EL1_TF1) { > >> + write_sysreg_s(0, SYS_TFSR_EL1); > >> + isb(); > > While in general we use ISB after a sysreg update, I haven't convinced > > myself it's needed here. There's no side-effect to updating this reg and > > a subsequent TFSR access should see the new value. > > Why there is no side-effect?
Catalin's saying that the value of TFSR_EL1 doesn't affect anything other than a read of TFSR_EL1, i.e. there are no indirect reads of TFSR_EL1 where the value has an effect, so there are no side-effects.
Looking at the ARM ARM, no synchronization is requires from a direct write to an indirect write (per ARM DDI 0487F.c table D13-1), so I agree that we don't need the ISB here so long as there are no indirect reads.
Are you aware of cases where the TFSR_EL1 value is read other than by an MRS? e.g. are there any cases where checks are elided if TF1 is set? If so, we may need the ISB to order the direct write against subsequent indirect reads.
Thanks, Mark.
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