Messages in this thread Patch in this message | | | From | Zhiqiang Hou <> | Subject | [PATCH 3/7] dt-bindings: pci: layerscape-pci: Add a optional property big-endian | Date | Mon, 7 Sep 2020 13:37:57 +0800 |
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From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
This property is to indicate the endianness when accessing the PEX_LUT and PF register block, so if these registers are implemented in big-endian, specify this property.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> --- Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index 99a386ea691c..2236d3f3089b 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -37,6 +37,10 @@ Required properties: of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly. +Optional properties: +- big-endian: If the PEX_LUT and PF register block is in big-endian, specify + this property. + Example: pcie@3400000 { -- 2.17.1
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