Messages in this thread | | | Date | Fri, 4 Sep 2020 16:19:12 -0300 | From | Arnaldo Carvalho de Melo <> | Subject | Re: [PATCH 2/4] perf vendor events amd: Add ITLB Instruction Fetch Hits event for zen1 |
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Em Wed, Sep 02, 2020 at 11:03:38PM -0700, Ian Rogers escreveu: > On Tue, Sep 1, 2020 at 3:10 PM Kim Phillips <kim.phillips@amd.com> wrote: > > > > The ITLB Instruction Fetch Hits event isn't documented even in > > later zen1 PPRs, but it seems to count correctly on zen1 hardware. > > > > Add it to zen1 group so zen1 users can use the upcoming IC Fetch Miss > > Ratio Metric. > > > > The IF1G, 1IF2M, IF4K (Instruction fetches to a 1 GB, 2 MB, and 4K page) > > unit masks are not added because unlike zen2 hardware, zen1 hardware > > counts all its unit masks with a 0 unit mask according to the old > > convention: > > > > zen1$ perf stat -e cpu/event=0x94/,cpu/event=0x94,umask=0xff/ sleep 1 > > > > Performance counter stats for 'sleep 1': > > > > 211,318 cpu/event=0x94/u > > 211,318 cpu/event=0x94,umask=0xff/u > > > > Rome/zen2: > > > > zen2$ perf stat -e cpu/event=0x94/,cpu/event=0x94,umask=0xff/ sleep 1 > > > > Performance counter stats for 'sleep 1': > > > > 0 cpu/event=0x94/u > > 190,744 cpu/event=0x94,umask=0xff/u > > > > Signed-off-by: Kim Phillips <kim.phillips@amd.com> > > Acked-by: Ian Rogers <irogers@google.com>
Thanks, applied.
- Arnaldo
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