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SubjectRe: [PATCH v13 08/15] mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR mode
On 30/09/20 06:50AM, Tudor.Ambarus@microchip.com wrote:
> On 9/16/20 3:44 PM, Pratyush Yadav wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > Some controllers, like the cadence qspi controller, have trouble reading
> > only 1 byte in DTR mode. So, do 2 byte reads for SR and FSR commands in
>
> did you get garbage when reading only one byte?

Yes.

> > DTR mode, and then discard the second byte.
> >
> > Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
> > ---
> > drivers/mtd/spi-nor/core.c | 15 +++++++++++++--
> > 1 file changed, 13 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> > index 88c9e18067f4..87c568debf14 100644
> > --- a/drivers/mtd/spi-nor/core.c
> > +++ b/drivers/mtd/spi-nor/core.c
> > @@ -368,7 +368,7 @@ int spi_nor_write_disable(struct spi_nor *nor)
> > * spi_nor_read_sr() - Read the Status Register.
> > * @nor: pointer to 'struct spi_nor'.
> > * @sr: pointer to a DMA-able buffer where the value of the
> > - * Status Register will be written.
> > + * Status Register will be written. Should be at least 2 bytes.
> > *
> > * Return: 0 on success, -errno otherwise.
> > */
> > @@ -386,6 +386,11 @@ static int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
> > if (spi_nor_protocol_is_dtr(nor->reg_proto)) {
> > op.addr.nbytes = nor->params->rdsr_addr_nbytes;
> > op.dummy.nbytes = nor->params->rdsr_dummy;
> > + /*
> > + * We don't want to read only one byte in DTR mode. So,
> > + * read 2 and then discard the second byte.
> > + */
> > + op.data.nbytes = 2;
>
> just for octal dtr, but should be fine if you update the previous patch

Ok.

--
Regards,
Pratyush Yadav
Texas Instruments India

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