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SubjectRe: dsa: mv88e6xxx: serdes link without phy
Date

On 1/10/20 2:24 pm, Andrew Lunn wrote:
>>                         port@8 {
>>                                 reg = <8>;
>>                                 label = "internal8";
>>                                 phy-mode = "rgmii-id";
>>                                 fixed-link {
>>                                         speed = <1000>;
>>                                         full-duplex;
>>                                 };
>>                         };
>>                         port@9 {
>>                                 reg = <9>;
>>                                 label = "internal9";
>>                                 phy-mode = "rgmii-id";
>>                                 fixed-link {
>>                                         speed = <1000>;
>>                                         full-duplex;
>>                                 };
>>                         };
>> The problem is that by declaring ports 8 & 9 as fixed link the driver
>> sets the ForcedLink in the PCS control register. Which mostly works.
>> Except if I add a chassis controller while the system is running (or one
>> is rebooted) then the newly added controller doesn't see a link on the
>> serdes.
> Hi Chris
>
> You say SERDES here, but in DT you have rgmii-id?
Yeah that's mostly because it was copied from the CPU port (which is
RGMII with internal delay). The Marvell datasheet says "SERDES" so I
wasn't really sure what to put here
> Can you run 1000Base-X over these links?
With some reading "1000base-x" does seem the right thing to say here.
It's even what is reflected in the CMODE field for those ports.
> If you can, it is probably
> worth chatting to Russell King about using inband-signalling, and what
> is needed to make it work without having back to back SFPs. If i
> remember correctly, Russell has said not much is actually needed.

That'd be ideal. The sticking point seems to be allowing it to have no PHY.
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