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Subject[tip: perf/core] perf/x86/intel: Add Jasper Lake support
The following commit has been merged into the perf/core branch of tip:

Commit-ID: dbfd638889a0396f5fe14ff3cc2263ec1e1cac62
Gitweb: https://git.kernel.org/tip/dbfd638889a0396f5fe14ff3cc2263ec1e1cac62
Author: Kan Liang <kan.liang@linux.intel.com>
AuthorDate: Mon, 28 Sep 2020 05:30:41 -07:00
Committer: Peter Zijlstra <peterz@infradead.org>
CommitterDate: Tue, 29 Sep 2020 09:57:01 +02:00

perf/x86/intel: Add Jasper Lake support

The Jasper Lake processor is also a Tremont microarchitecture. From the
perspective of Intel PMU, there is nothing changed compared with
Elkhart Lake.
Share the perf code with Elkhart Lake.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1601296242-32763-1-git-send-email-kan.liang@linux.intel.com
---
arch/x86/events/intel/core.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index c72e490..75dea67 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -5135,6 +5135,7 @@ __init int intel_pmu_init(void)

case INTEL_FAM6_ATOM_TREMONT_D:
case INTEL_FAM6_ATOM_TREMONT:
+ case INTEL_FAM6_ATOM_TREMONT_L:
x86_pmu.late_ack = true;
memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
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