Messages in this thread |  | | Date | Wed, 30 Sep 2020 15:51:03 -0300 | From | Jason Gunthorpe <> | Subject | Re: [PATCH v3 05/18] dmaengine: idxd: add IMS support in base driver |
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On Wed, Sep 30, 2020 at 08:47:00PM +0200, Thomas Gleixner wrote:
> > + pci_read_config_dword(pdev, SIOVCAP(dvsec), &val32); > > + if ((val32 & 0x1) && idxd->hw.gen_cap.max_ims_mult) { > > + idxd->ims_size = idxd->hw.gen_cap.max_ims_mult * 256ULL; > > + dev_dbg(dev, "IMS size: %u\n", idxd->ims_size); > > + set_bit(IDXD_FLAG_SIOV_SUPPORTED, &idxd->flags); > > + dev_dbg(&pdev->dev, "IMS supported for device\n"); > > + return; > > + } > > + > > + dev_dbg(&pdev->dev, "SIOV unsupported for device\n"); > > It's really hard to find the code inside all of this dev_dbg() > noise. But why is this capability check done in this driver? Is this > capability stuff really IDXD specific or is the next device which > supports this going to copy and pasta the above?
It is the weirdest thing, IMHO. Intel defined a dvsec cap in their SIOV cookbook, but as far as I can see it serves no purpose at all.
Last time I asked I got some unclear mumbling about "OEMs".
I expect you'll see all Intel drivers copying this code.
Jason
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