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SubjectRE: [PATCH v2] PCI: Cadence: Add quirk for Gen2 controller to do autonomous speed change.
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Hi Kishon,

> -----Original Message-----
> From: Kishon Vijay Abraham I <kishon@ti.com>
> Sent: Thursday, September 24, 2020 9:45 AM
> To: Athani Nadeem Ladkhan <nadeem@cadence.com>; Tom Joseph
> <tjoseph@cadence.com>; lorenzo.pieralisi@arm.com; robh@kernel.org;
> bhelgaas@google.com; linux-pci@vger.kernel.org; linux-
> kernel@vger.kernel.org
> Cc: Milind Parab <mparab@cadence.com>; Swapnil Kashinath Jakhade
> <sjakhade@cadence.com>
> Subject: Re: [PATCH v2] PCI: Cadence: Add quirk for Gen2 controller to do
> autonomous speed change.
>
> EXTERNAL MAIL
>
>
> Hi Nadeem,
>
> On 24/09/20 12:04 am, Nadeem Athani wrote:
> > Cadence controller will not initiate autonomous speed change if
> > strapped as Gen2. The Retrain bit is set as a quirk to trigger this
> > speed change.
> >
> > Signed-off-by: Nadeem Athani <nadeem@cadence.com>
> > ---
> > drivers/pci/controller/cadence/pcie-cadence-host.c | 14 ++++++++++++++
> > drivers/pci/controller/cadence/pcie-cadence.h | 15 +++++++++++++++
> > 2 files changed, 29 insertions(+)
> >
> > diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c
> > b/drivers/pci/controller/cadence/pcie-cadence-host.c
> > index 4550e0d469ca..a2317614268d 100644
> > --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> > +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> > @@ -83,6 +83,9 @@ static int cdns_pcie_host_init_root_port(struct
> cdns_pcie_rc *rc)
> > struct cdns_pcie *pcie = &rc->pcie;
> > u32 value, ctrl;
> > u32 id;
> > + u32 link_cap = CDNS_PCIE_LINK_CAP_OFFSET;
> > + u8 sls;
> > + u16 lnk_ctl;
> >
> > /*
> > * Set the root complex BAR configuration register:
> > @@ -111,6 +114,17 @@ static int cdns_pcie_host_init_root_port(struct
> cdns_pcie_rc *rc)
> > if (rc->device_id != 0xffff)
> > cdns_pcie_rp_writew(pcie, PCI_DEVICE_ID, rc->device_id);
> >
> > + /* Quirk to enable autonomous speed change for GEN2 controller */
> > + /* Reading Supported Link Speed value */
> > + sls = PCI_EXP_LNKCAP_SLS &
> > + cdns_pcie_rp_readb(pcie, link_cap + PCI_EXP_LNKCAP);
> > + if (sls == PCI_EXP_LNKCAP_SLS_5_0GB) {
> > + /* Since this a Gen2 controller, set Retrain Link(RL) bit */
> > + lnk_ctl = cdns_pcie_rp_readw(pcie, link_cap +
> PCI_EXP_LNKCTL);
> > + lnk_ctl |= PCI_EXP_LNKCTL_RL;
> > + cdns_pcie_rp_writew(pcie, link_cap + PCI_EXP_LNKCTL,
> lnk_ctl);
> > + }
>
> Is this workaround required for all Cadence controller? If not, enable this
> workaround only for versions which doesn't do autonomous speed change.
No. This is taken care in patch version 3.
>
> I think this workaround should also be applied only after checking for link
> status (cdns_pcie_link_up()).
Yes. This is taken care in patch version 3.
>
> And this is also applicable for GEN3/GEN4 controller. So the check should be
> to see the capability of the connected PCIe device and not the controller
> itself.
This is taken care in patch version 3.
>
> Thanks
> Kishon
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